M29W008ET-70N6E ,8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash MemoryFEATURES SUMMARY■ ACCESS TIMES: 70ns, 90ns■ PROGRAMMING TIME: 10µs per Byte typical■ PROGRAM/ERASE ..
M29W008T ,NOT FOR NEW DESIGNLogic Diagram– Read and Program another Block duringErase SuspendLOW POWER CONSUMPTION– Stand-by an ..
M29W008T-120N5TR ,8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash MemoryLogic Diagram– Read and Program another Block duringErase SuspendLOW POWER CONSUMPTION– Stand-by an ..
M29W010B ,1 MBIT (128KB X8, UNIFORM BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYLogic Diagram, and Table 1, SignalErase Controller is programming or erasing duringNames, for a bri ..
M29W010B45K1 , 1 Mbit 128Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
M29W010B-45K1 , 1 Mbit 128Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
M50747-161SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50747-2B4SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50747-2B4SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50940-303SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50941-330SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50FLW040A ,4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (FWH/LPC Interface) . 7Table ..
M29W008ET-70N6E
8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory
Rev 0.1
June 2005 1/43
M29W008ET
M29W008EB8 Mbit (1Mb x 8, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY ACCESS TIMES: 70ns, 90ns PROGRAMMING TIME: 10µs per Byte typical PROGRAM/ERASE CONTROLLER (P/E.C.) Embedded Byte Program Algorithm Status Register bits and Ready/Busy
Output 19 MEMORY BLOCKS 1 Boot Block (Top or Bottom location) 2 Parameter and 16 Main Blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTIPLE BLOCK PROTECTION/
TEMPORARY UNPROTECTION MODE ERASE SUSPEND and RESUME MODES LOW POWER CONSUMPTION Standby and Automatic Standby modes 100,000 PROGRAM/ERASE CYCLES per
BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h M29W008ET Device Code: D2h M29W008EB Device Code: DCh ECOPACK® TSOP40 PACKAGE
Figure 1. Package
M29W008ET, M29W008EB2/43
Contents Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1 Address Inputs (A0-A19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Data Input/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.7 Reset/Block Temporary Unprotect Input (RP) . . . . . . . . . . . . . . . . . . . . . . . . .11
2.8 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.9 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.1 Standard bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 Block Protection and Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
M29W008ET, M29W008EB 3/43
4.8 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.10 Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Appendix A Block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Appendix B Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
M29W008ET, M29W008EB4/43
List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 19
Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Write AC Characteristics, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Write AC Characteristics, E Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . 32
Table 15. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Top Boot Block Addresses, M29W008ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. Bottom Boot Block Addresses, M29W008EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. Programmer Technique Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 19. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
M29W008ET, M29W008EB
5/43
List of figures
Figure 1. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Block Addresses (Top Boot Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Block Addresses (Bottom Boot Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Write AC Waveforms, E Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . . . 32
Figure 15. Programmer Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 16. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. In-System Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 18. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1 Summary description M29W008ET, M29W008EB
6/43
1 Summary description
The M29W008E is a 8 Mbit (1Mb x 8) non-volatile Flash memory that can be read, erased at
block, multi-block or chip level and programmed at Byte level. These operations are performed
using a single 2.7V to 3.6V VCC supply voltage. For Program and Erase operations the
necessary high voltages are generated internally. The device can also be programmed using
standard programming equipment.
The memory is divided into blocks that are asymmetrically arranged. Both M29W008ET and
M29W008EB devices have an array of 19 blocks composed of one Boot Block of 16 KBytes,
two Parameter Blocks of 8 KBytes, one Main Block of 32 KBytes and fifteen Main Blocks of 64
KBytes. In the M29W008ET, the Boot Block is located at the top of the memory address space
while in the M29W008EB, it is located at the bottom. The memory maps are showed in
Figure 4: Block Addresses (Top Boot Block) and Figure 5: Block Addresses (Bottom Boot
Block). Each block can be erased and reprogrammed independently so it is possible to
preserve valid data while old data is erased. Program and Erase commands are written to the
Command Interface of the memory. An on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by taking care of all of the special operations
that are required to update the memory contents. The end of a program or erase operation can
be detected and any error conditions identified. Erase operations in one block can be
temporarily suspended in order to read from or program in blocks that are not being erased.
Each block can be programmed and erased over 100,000 cycles.
Each block can be protected independently to prevent accidental Program or Erase commands
from modifying the memory. All previously protected blocks can be temporarily unprotected.
In order to meet environmental requirements, ST offers this device in a TSOP40 (10 x 20mm)
ECOPACK® package. ECOPACK® packages are Lead-free and RoHS compliant. The category
of second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK
specifications are available at: .
The device is offered in package and supplied with all the bits erased (set to ’1’).
Table 1. Signal Names
M29W008ET, M29W008EB 1 Summary description
7/43
Figure 2. Logic diagram
Figure 3. TSOP Connections
1 Summary description M29W008ET, M29W008EB
8/43
Figure 4. Block Addresses (Top Boot Block)
M29W008ET, M29W008EB 1 Summary description
9/43
Figure 5. Block Addresses (Bottom Boot Block)
2 Signal descriptions M29W008ET, M29W008EB
10/43
2 Signal descriptions
See Figure 2: Logic diagram and Table 1: Signal Names, for a brief overview of the signals
connected to this device.
2.1 Address Inputs (A0-A19)
The address inputs for the memory array are latched during a Bus Write operation on the falling
edge of Chip Enable, E or Write Enable, W. When A9 is raised to VID, either a Read Electronic
Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or
Block Unprotection is enabled depending on the combination of levels on A0, A1 A6, A12 and
A15.
2.2 Data Input/Outputs (DQ0-DQ7)
During Bus Write operations, the Data Inputs/Outputs input the data to be programmed in the
memory array or a command to be written to the Command Interface. Both are latched on the
rising edge of Chip Enable, E or Write Enable, W. The Data Inputs/Outputs output the data
stored at the selected address during a Bus Read operation, the Electronic Signature
(Manufacturer or Device codes), the Block Protection Status or the Data Polling bit (DQ7),
Toggle Bits (DQ6) and DQ2), Error bit (DQ5) or Erase Timer bit (DQ3) of the Status Register.
Outputs are valid when Chip Enable, E and Output Enable, G are active. The output is high
impedance when the chip is deselected or the outputs are disabled and when RP is Low.
2.3 Chip Enable (E)
The Chip Enable, E, activates the memory control logic, input buffers, decoders and sense
amplifiers. When Chip Enable is High, VIH, the memory is deselected and the power
consumption is reduced to the Standby level. The Chip Enable, E, can also be used to control
Write operations to the command register and to the memory array, while W remains Low. The
Chip Enable must be forced to VID during Block Unprotection operations.
2.4 Output Enable (G)
The Output Enable, G , gates the outputs through the data buffers during a Bus Read operation.
When G is High, VIH, the outputs are high impedance. G must be forced to VID during Block
Protection and Unprotection operations.
2.5 Write Enable (W)
This Write Enable, W, controls write operations of the memory’s Command Interface.
M29W008ET, M29W008EB 2 Signal descriptions
11/43
2.6 Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the memory
array can be read. Ready/Busy is high impedance during Read mode, Auto Select mode and
Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high impedance. See Table 13: Reset/Block Temporary Unprotect AC Characteristics
and Figure 13: Reset/Block Temporary Unprotect AC Waveforms.
During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low
during Read/Reset commands or Hardware Resets until the memory is ready to enter Read
mode.
2.7 Reset/Block Temporary Unprotect Input (RP)
The Reset/Block Temporary Unprotect input, RP , can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all blocks that have been previously protected.
A Hardware Reset is achieved by holding RP Low, VIL for at least tPLPX. After Reset/Block
Temporary Unprotect goes High, VIH, if the device is in Read or Standby mode, it will be ready
for new operations tPHEL after the rising edge of RP. If the device is in Erase, Erase Suspend or
Program mode, the Hardware Reset will last tPLYH during which the RB signal will be held at
VIL. The end of the memory Hardware Reset will be indicated by the rising edge of RB. A
Hardware Reset during an Erase or Program operation will corrupt the data being programmed
or the blocks being erased. See Table 13: Reset/Block Temporary Unprotect AC
Characteristics and Figure 13: Reset/Block Temporary Unprotect AC Waveforms.
Holding RP at VID will temporarily unprotect the previously protected blocks in the memory.
Program and Erase operations on all blocks will be possible. The transition of RP from VIH to
VID must slower than tPHPHH.
When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected.
2.8 VCC Supply Voltage
The power supply for all operations (Read, Program and Erase).
A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths must
be sufficient to carry the currents required during program and erase operations, ICC3
2.9 VSS Ground
VSS is the reference for all voltage measurements.
3 Bus Operations M29W008ET, M29W008EB
12/43
3 Bus Operations
There are 5 standard bus operations that control the device. These are Bus Read, us Write,
Output Disable, Standby and Automatic Standby. See Table 2: Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory
and do not affect the bus operations.
3.1 Standard bus operations
3.1.1 Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register or the Block Protection Status. Both Chip Enable E and Output
Enable G must be Low in order to read the output of the memory. A new Bus Read operation is
initiated either on the falling edge of Chip Enable, E, or on any address transition with E at VIL.
See Figure 10: Read Mode AC Waveforms, and Table 10: Read AC Characteristics for details
of the timing requirements.
3.1.2 Bus Write
Bus Write operations are used to write to the Command Interface or to latch input data to be
programmed. A valid Bus Write operation begins by setting the desired address on the Address
Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first.
Output Enable must remain High, VIH, during the whole Bus Write operation.
See Figures 11 and 12, Write AC Waveforms and Tables 11 and 12, Write AC Characteristics,
for details of the timing requirements.
3.1.3 Output Disable
The data outputs are high impedance when the Output Enable G is High with Write Enable W
High.
3.1.4 Standby
The memory is in Standby mode when Chip Enable, E, is High and the Program/Erase
Controller is idle. The Supply Current is reduced to the Standby Supply Current, ICC2, and the
outputs are high impedance, independent of the Output Enable G or Write Enable W inputs.
3.1.5 Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and if the bus is inactive (no address
transition, E = VIL) during 150ns or more, the memory automatically enters a Automatic
Standby mode where the Supply Current is reduced to the Standby Supply Current, ICC2. The
Inputs/Outputs will still output data if a Bus Read operation is in progress.
M29W008ET, M29W008EB 3 Bus Operations
13/43
3.2 Special bus operations
Additional bus operations can be performed to read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming
equipment and are not usually used in applications. They require VID to be applied to some
pins.
3.2.1 Read Electronic Signature
The memory has two codes, the Manufacturer code and the Device code, that can be read to
identify the memory.
These codes allow programming equipment or applications to automatically match their
interface to the characteristics of the M29W008E.
The electronic Signature is output either by applying the signals listed in Table 2: Bus
Operations or by issuing an Auto Select command (see Section 4.2: Auto Select command).
3.2.2 Block Protection and Unprotection
Each block can be individually protected against accidental Program or Erase using
programming equipment. Protected blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on
programming equipment (Programmer Technique) and the other for in-system use (In-System
Technique). Block Protect and Chip Unprotect operations are described in Appendix B: Block
protection.
Table 2. Bus Operations X = VIL or VIH.
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4 Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a valid
sequence of Bus Write operations will result in the memory returning to Read mode. The long
command sequences are imposed to maximize data security. All commands start with two
coded cycles which unlock the Command Interface.
Seven commands are available: Read/Reset, Auto Select (to read the Electronic Signature and
the Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase
Resume (see Table 3: Commands).
4.1 Read/Reset command
The Read/Reset command returns the memory to its Read mode where it behaves like a ROM
or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one
or three Bus Write operations can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. Once the program or erase
operation has started the Read/Reset command is no longer accepted. The Read/Reset
command will not abort an Erase operation when issued while in Erase Suspend.
4.2 Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code and the
Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto
Select command. Once the Auto Select command is issued the memory remains in Auto Select
mode until another command is issued.
From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH.
The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The
other address bits may be set to either VIL or VIH.
The Block Protection Status of each block can be read using a Bus Read operation with A0 =
VIL, A1 = VIH, and A13-A19 specifying the address of the block. The other address bits may be
set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/
Outputs DQ0-DQ7, otherwise 00h is output.
4.3 Program command
The Program command can be used to program a value to one address in the memory array at
a time. The command requires four Bus Write operations, the final write operation latches the
address and data and starts the Program/Erase Controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
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During the program operation the memory will ignore all commands. It is not possible to issue
any command to abort or pause the operation. Typical program times are given in Table4:
Program, Erase Times and Program, Erase Endurance Cycles. Bus Read operations during
the program operation will output the Status Register on the Data Inputs/Outputs. See
Section 5: Status register for more details.
After the program operation has completed the memory will return to the Read mode, unless an
error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
4.4 Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the access time to the device is long (as with some
EPROM programmers) considerable time saving can be made by using these commands.
Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be read
as if in Read mode.
4.5 Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in memory at a
time. The command requires two Bus Write operations, the final write operation latches the
address and data and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass Program command behaves identically to the
Program operation using the Program command. A protected block cannot be programmed;
the operation cannot be aborted and the Status Register is read. Errors must be reset using the
Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program
command for details on the behavior.
4.6 Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock
Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset
command. Read/Reset command does not exit from Unlock Bypass Mode.
4.7 Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can be
selected by repeating the sixth Bus Write operation using the address of the additional block.
The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus
Write operation. Once the Program/Erase Controller starts it is not possible to select any more
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blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected. The Status Register can be read after the
sixth Bus Write operation. See the Status Register for details on how to identify if the Program/
Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to start
but will terminate within about 100µs, leaving the data unchanged. No error condition is given
when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical program times are given in Table 4: Program, Erase Times and
Program, Erase Endurance Cycles. All Bus Read operations during the Block Erase operation
will output the Status Register on the Data Inputs/Outputs. See the section on the Status
Register for more details.
After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and return
to Read mode.
The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
4.8 Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are
required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all of
the blocks are protected the Chip Erase operation appears to start but will terminate within
about 100µs, leaving the data unchanged. No error condition is given when protected blocks
are ignored.
During the erase operation the memory will ignore all commands. It is not possible to issue any
command to abort the operation. Typical program times are given in Table 4: Program, Erase
Times and Program, Erase Endurance Cycles. All Bus Read operations during the Chip Erase
operation will output the Status Register on the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read Mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
4.9 Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase operation
and return the memory to Read mode. The command requires one Bus Write operation.
The Program/Erase Controller will suspend within the Erase Suspend Latency Time after the
Erase Suspend Command is issued (see Table 4: Program, Erase Times and Program, Erase
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Endurance Cycles). Once the Program/Erase Controller has stopped the memory will be set to
Read mode and the Erase will be suspended. If the Erase Suspend command is issued during
the period when the memory is waiting for an additional block (before the Program/Erase
Controller starts) then the Erase is suspended immediately and will start immediately when the
Erase Resume Command is issued. It is not possible to select any further blocks to erase after
the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any attempt
is made to program in a protected block or in the suspended block then the Program command
is ignored and the data remains unchanged. The Status Register is not read and no error
condition is given. Reading from blocks that are being erased will output the Status Register.
It is also possible to issue the Auto Select, during an Erase Suspend. The Read/Reset
command must be issued to return the device to Read Array mode before the Resume
command will be accepted.
4.10 Erase Resume Command
The Erase Resume command must be used to restart the Program/Erase Controller from
Erase Suspend. An erase can be suspended and resumed more than once.
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Table 3. Commands Commands not interpreted in this table will default to read array mode. X = Don't Care. PA = Program Address, PD = Program Data, BA = Block Address, AB = Additional Block. For Coded cycles address inputs A15-A19 are don't care. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting
any new operation (see Table 10: Read AC Characteristics). The first cycles of the Read/Reset and Auto Select commands are followed by read operations. Any number of read cycles
can occur after the command cycles. Signature Address bits A0, A1, at VIL will output the Manufacturer Code (20h). Address bits A0 at VIH and A1, at VIL will
output the Device Code. Block Protection Address: A0, at VIL, A1 at VIH and A13-A19 within the Block will output the Block Protection status. Read Data Polling, Toggle bits or RB until Erase completes. Optional, Additional Block (AB) addresses must be entered within the erase time-out delay after last write entry, time-out
status can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data
Polling or Toggle bit until Erase has completed or is suspended.
10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
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Table 4. Program, Erase Times and Program, Erase Endurance Cycles Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VCC.
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5 Status register
The status of the Program/Erase Controller during command execution is indicated by bit DQ7
(Data Polling bit), Toggle bits DQ6 and DQ2 and Error bits DQ3 and DQ5. Any attempt to read
the memory array during Program or Erase command execution will automatically output these
five Status Register bits. The Program/Erase Controller automatically sets bits DQ2, DQ3,
DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should
be masked (see Table 5: Status Register Bits).
5.1 Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory returns
to Read mode and Bus Read operations from the address just programmed output DQ7, not its
complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within
a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/
Erase Controller has suspended the Erase operation.
Figure 6: Data Polling Flowchart gives an example of how to use the Data Polling Bit. A Valid
Address is the address being programmed or an address within the block being erased.
5.2 Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully
completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on
DQ6 when the Status Register is read.
During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the operation
the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The T oggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
If any attempt is made to erase a protected block, the operation is aborted, no error is signalled
and DQ6 toggles for approximately 100µs. If any attempt is made to program a protected block
or a suspended block, the operation is aborted, no error is signalled and DQ6 toggles for
approximately 1µs.
Figure 7: Data Toggle Flowchart gives an example of how to use the Data Toggle bit.
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5.3 Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register is
read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do
so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of
the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’
5.4 Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase
Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’
and additional blocks to be erased may be written to the Command Interface. The Erase Timer
Bit is output on DQ3 when the Status Register is read.
5.5 Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase
operations. The Alternative T oggle Bit is output on DQ2 when the Status Register is read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc.,
with successive Bus Read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation completes
the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if in
Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within
blocks that have not erased correctly. The Alternative Toggle Bit does not change if the
addressed block has erased correctly.
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Table 5. Status Register Bits
Note: Unspecified data bits should be ignored.
Figure 6. Data Polling Flowchart
