MAX14830ETM+ ,Quad Serial UART with 128-Word FIFOsPin Description....... 15Detailed Description... 18Receive and Transmit FIFOs . . . . . . . . . . . ..
MAX1483CPA ,20A / 1.8-Unit-Load / Slew-Rate-Limited RS-485 TransceiversMAX1482/MAX148319-0367; Rev 0; 2/95120µA, ⁄ -Unit-Load, Slew-Rate-Limited8RS-485 Transceivers______ ..
MAX1483CPA+ ,20µA, 1/8-Unit-Load, Slew-Rate-Limited, RS-485 TransceiversFeaturesThe MAX1482 and MAX1483 are low-power trans-♦ Low 20µA Operating Currentceivers for RS-485 ..
MAX1483CSA ,20A / 1.8-Unit-Load / Slew-Rate-Limited RS-485 TransceiversGeneral Description ________
MAX1483CSA ,20A / 1.8-Unit-Load / Slew-Rate-Limited RS-485 TransceiversApplicationsMAX1483CPA 0°C to +70°C 8 Plastic DIPIndustrial-Control Local Area NetworksMAX1483CSA 0 ..
MAX1483CSA ,20A / 1.8-Unit-Load / Slew-Rate-Limited RS-485 TransceiversGeneral Description ________
MAX4072AUA ,Bidirectional / High-Side / Current-Sense Amplifiers with ReferenceMAX4069–MAX407219-2423; Rev 2; 1/03Bidirectional, High-Side, Current-SenseAmplifiers with Reference
MAX4072AUA+ ,Bidirectional, High-Side, Current-Sense Amplifiers with ReferenceFeaturesThe MAX4069–MAX4072 low-cost, bidirectional, high-♦ Bidirectional, Compact, Current-Sense S ..
MAX4073FAUT ,Low-Cost, SC70, Voltage-Output, High-Side Current-Sense AmplifierFeaturesThe MAX4073 low-cost, high-side current-sense ampli-♦ Low-Cost, Compact, Current-Sense Solu ..
MAX4073FAUT+T ,Low-Cost, SC70, Voltage-Output, High-Side Current-Sense Amplifierfeatures a voltage output that eliminates the need♦ Three Gain Versions Availablefor gain-setting r ..
MAX4073FAUT-T ,Low-Cost, SC70, Voltage-Output, High-Side Current-Sense AmplifierApplications0.1µ FCell PhonesMAX4073T/F/HNotebook ComputersPortable/Battery-Powered SystemsA/D LOAD ..
MAX4073FAXK ,Low-Cost, SC70, Voltage-Output, High-Side Current-Sense Amplifier MAX4073T/F/HLow-Cost, SC70, Voltage-Output, High-Side Current-Sense Amplifier
MAX14830ETM+
Quad Serial UART with 128-Word FIFOs
General DescriptionThe MAX14830 is an advanced quad universal asynchro-
nous receiver-transmitter (UART), each UART having
128 words of receive and transmit first-in/first-out (FIFO)
and a high-speed serial peripheral interface (SPI) or I2C
controller interface. A PLL and fractional baud-rate
generators allow a high degree of flexibility in baud-rate
programming and reference clock selection.
Each of the four UARTs is selected by in-band SPI/I2C
addressing. Logic-level translation on the transceiver and
controller interfaces allows ease of interfacing to micro-
controllers, FPGAs, and transceivers that are powered by
differing supply voltages.
Extensive features simplify transceiver control in
half-duplex communication applications. The MAX14830
features the ability to synchronize the start of individual
UART’s transmission by SPI-based triggering. On-board
timers allow programming of delays between transmitters
as well as clock generation on GPIOs.
The 128-word FIFOs have advanced FIFO control
reducing host processor data flow management.
The MAX14830 is available in a 48-pin TQFN (7mm 7mm) package and is specified to operate. over the
extended -40°C to +85°C temperature range.
Applications●Industrial Control Systems●Programmable Logic Controllers (PLC)●IO-Link Master Controllers●Medical Systems●Point-of-Sales Systems●Airplane Communication Buses
Beneits and Features●Bridges an SPI/MICROWIRE or I2C Microprocessor
Bus to an Asynchronous Interface like RS-485,
RS-232, or IrDASMSIR- and MIR-Compliant IrDA Encoder/DecoderLine Noise Indication Ensures Data Link Integrity●Deep, 128-Word Buffer and Automated Control
Features Help Offload Activity on the Microcontroller128-Word Transmit and Receive FIFOs per UART Transmitter Synchronization Through SPI CommandsAutomatic Hardware Flow Control Using RTS_ and
CTS_ Outputs and Inputs Automatic Software Flow Control (XON/XOFF) Auto Transceiver Direction Control Programmable Setup and Hold Times for Transceiver
Control Auto Transmitter Disable Half-Duplex Echo Suppression 9-Bit Multidrop-Mode Data Filtering
Special Character Detection
GPIO-Based Character Detection
Four Timers Routed to GPIOs
16 Flexible GPIOs with 20mA Drive Capability ●Saves Board SpaceTQFN (7mm x 7mm) Package●Fast Data Rates Allow Maximum System Flexibility
Across Interface Standards6Mbaud (max) Data Rate in 16x Sampling Mode 12/24Mbaud (max) Data Rate in 2x/4x Rate Modes High-Resolution Programmable Baud-Rate SPI Up to 26MHz Clock Rate Fast Mode Plus (Pm+) I2C Up to 1MHz ●Integrated Internal Oscillator Eliminates the Need for
an External Oscillator and Reduces the BOM Cost Fractional Baud-Rate Generators, Predivider, and
Phase-Locked Loop (PLL) Logic-Level Translation Down to 1.61V on the Con-
troller and Transceiver Interfaces Ensures System
CompatibilityRegister Compatible with MAX3107, MAX3108,
MAX3109
Typical Operating Circuit and Ordering Information appear
at end of data sheet.IrDA is a registered service mark of Infrared Data Association
Corporation.
MAX14830Quad Serial UART with 128-Word FIFOs
EVALUATION KIT AVAILABLE
General Description............................................................................1
Applications ..................................................................................1
Benefits and Features ..........................................................................1
Functional Diagram ............................................................................7
Absolute Maximum Ratings......................................................................8
Package Thermal Characteristics .................................................................8
DC Electrical Characteristics.....................................................................8
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Test Circuits/Timing Diagrams...................................................................13
Typical Operating Characteristics ................................................................14
Pin Configuration .............................................................................15
Pin Description...............................................................................15
Detailed Description...........................................................................18
Receive and Transmit FIFOs ..................................................................18
Transmitter Operation........................................................................18
Receiver Operation..........................................................................19
Line Noise Indication.........................................................................20
Clocking and Baud-Rate Generation ............................................................20
Crystal Oscillator .........................................................................20
External Clock Source.....................................................................20
PLL and Predivider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Fractional Baud-Rate Generators...............................................................21
2x and 4x Rate Modes .......................................................................21
Low-Frequency Timer........................................................................22
UART Clock to GPIO ........................................................................22
Multidrop Mode.............................................................................22
Auto Data Filtering in Multidrop Mode.........................................................22
Auto Transceiver Direction Control..............................................................22
Transmitter Triggering and Synchronization.......................................................23
Transmitter Synchronization ................................................................23
Intrachip and Interchip Synchronization .......................................................23
Delayed Triggering........................................................................23
Trigger Accuracy .........................................................................24
Synchronization Accuracy..................................................................24
Auto Transmitter Disable......................................................................24
Echo Suppression...........................................................................24
Auto Hardware Flow Control...................................................................26
TABLE OF CONTENTSMAX14830Quad Serial UART with 128-Word FIFOs
AutoCTS Control .........................................................................26
FIFO Interrupt Triggering .....................................................................26
Auto Software (XON/XOFF) Flow Control ........................................................26
Transmitter Flow Control ...................................................................27
Receiver Overflow Control..................................................................27
Power-Up and IRQ ..........................................................................27
Shutdown Mode ............................................................................27
Interrupt Structure...........................................................................27
Interrupt Enabling.........................................................................28
Interrupt Clearing.........................................................................28
Register Map ................................................................................28
Detailed Register Descriptions.................................................................30
Serial Controller Interface ......................................................................58
SPI Interface...............................................................................58
MISO Operation..........................................................................58
SPI Burst Access.........................................................................58
Fast Read Cycle..........................................................................59
2C Interface ...............................................................................59
START, STOP, and Repeated START Conditions................................................59
Slave Address ...........................................................................60
Bit Transfer..............................................................................61
Single-Byte Write.........................................................................61
Burst Write..............................................................................61
Single-Byte Read.........................................................................62
Burst Read..............................................................................62
Acknowledge Bits.........................................................................63
Applications Information........................................................................63
Startup and Initialization......................................................................63
Low-Power Operation........................................................................63
Interrupts and Polling ........................................................................63
Logic-Level Translation.......................................................................63
IO-Link Application ..........................................................................63
Typical Operating Circuit .......................................................................65
Chip Information..............................................................................67
Ordering Information ..........................................................................67
Package Information ..........................................................................67
Revision History..............................................................................68
TABLE OF CONTENTS (continued)MAX14830Quad Serial UART with 128-Word FIFOs
Figure 1. I2C Timing Diagram ...................................................................13
Figure 2. SPI Timing Diagram ...................................................................13
Figure 3. Transmit FIFO Signals .................................................................18
Figure 4. Receive Data Format ..................................................................19
Figure 5. Receive FIFO ........................................................................19
Figure 6. Midbit Sampling ......................................................................19
Figure 7. Clock Selection Diagram................................................................20
Figure 8. 2x and 4x Baud Rates .................................................................21
Figure 9. GPIO_ Clock Pulse Generator...........................................................22
Figure 10. Auto Transceiver Direction Control.......................................................23
Figure 11. Setup and Hold times in Auto Transceiver Direction Control...................................23
Figure 12. Single Transmitter Trigger Accuracy......................................................24
Figure 13. Multiple Transmitter Synchronization Accuracy .............................................25
Figure 14. Echo Suppression Timing..............................................................25
Figure 15. Half-Duplex with Echo Suppression......................................................26
Figure 16. Simplified Interrupt Structure ...........................................................27
Figure 17. PLL Signal Path......................................................................51
Figure 18. SPI Write Cycle......................................................................58
Figure 19. SPI Read Cycle......................................................................59
Figure 20. SPI Fast Read Cycle..................................................................59
Figure 21. I2C START, STOP, and Repeated START Conditions ........................................60
Figure 22. Write Byte Sequence .................................................................61
Figure 23. Burst Write Sequence.................................................................61
Figure 24. Read Byte Sequence .................................................................62
Figure 25. Burst Read Sequence.................................................................62
Figure 26. Acknowledge Bits....................................................................63
Figure 27. Startup and Initialization Flow Chart......................................................63
Figure 28. Logic-Level Translation................................................................64
Figure 29. Interchip Synchronization..............................................................64
LIST OF FIGURESMAX14830Quad Serial UART with 128-Word FIFOs
Table 1. UART GPIO Assignments for GPIO Interrupts ...............................................38
Table 2. StopBits Truth Table.....................................................................41
Table 3. Length_ Truth Table.....................................................................41
Table 4. SwFlow_ Truth Table ...................................................................46
Table 5. UART GPIO Assignments for GPIO Configuration ............................................49
Table 6. UART GPIO Assignments for GPIO Input/Output Data.........................................50
Table 7. PLLFactor_ Selector Guide ..............................................................51
Table 8. GloblComnd Command Descriptions.......................................................54
Table 9. Extended Mode Addressing (SPI only) .....................................................54
Table 10. SPI Command Byte Configuration........................................................58
Table 11. SPI U1, U0 UART Selection.............................................................58
Table 12. I2C Address Map .....................................................................60
LIST OF TABLESMAX14830Quad Serial UART with 128-Word FIFOs
LIST OF REGISTERSRHR—Receive Hold Register ...................................................................30
THR—Transmit Hold Register ...................................................................30
IRQEn—IRQ Enable Register ...................................................................31
ISR—Interrupt Status Register ..................................................................32
LSRIntEn—Line Status Interrupt Enable Register....................................................33
LSR—Line Status Register .....................................................................34
SpclChrIntEn—Special Character Interrupt Enable Register ...........................................35
SpclCharInt—Special Character Interrupt Register...................................................36
STSIntEn—STS Interrupt Enable Register .........................................................37
STSInt—Status Interrupt Register................................................................38
MODE1 Register .............................................................................39
MODE2 Register .............................................................................40
LCR—Line Control Register......................................................................41
RxTimeOut—Receiver Timeout Register...........................................................42
HDplxDelay Register ..........................................................................42
IrDA Register ................................................................................43
FlowLvl—Flow Level Register ...................................................................44
FIFOTrigLvl—FIFO Interrupt Trigger Level Register ..................................................44
TxFIFOLvl—Transmit FIFO Level Register..........................................................45
RxFIFOLvl—Receive FIFO Level Register .........................................................45
FlowCtrl—Flow Control Register.................................................................45
XON1 Register...............................................................................47
XON2 Register...............................................................................47
XOFF1 Register ..............................................................................48
XOFF2 Register ..............................................................................48
GPIOConfg—GPIO Configuration Register.........................................................49
GPIOData—GPIO Data Register.................................................................50
PLLConfig—PLL Configuration Register...........................................................51
BRGConfig—Baud-Rate Generator Configuration Register............................................52
DIVLSB—Baud-Rate Generator LSB Divisor Register................................................52
DIVMSB—Baud-Rate Generator MSB Divisor Register...............................................52
CLKSource—Clock Source Register..............................................................53
GlobalIRQ—Global IRQ Register ................................................................53
GloblComnd—Global Command Register..........................................................54
TxSynch—Transmitter Synchronization Register.....................................................55
SynchDelay1—Synchronization Delay Register 1....................................................56
SynchDelay2—Synchronization Delay Register 2....................................................56
TIMER1—Timer Register 1 .....................................................................56
MAX14830Quad Serial UART with 128-Word FIFOs
REGISTERS
AND
CONTROL
TX0
RX0
GPIO0
GPIO3
UARTO
CTS0
RTS0
TX1
RX1
GPIO4
GPIO7
UART1
CTS1
RTS1
TX2
RX2
GPIO8
GPIO11
UART2
CTS2
RTS2
SPI AND
I2C
INTERFACE
LDO
PLLDIVIDER
LOGIC-LEVEL
TRANSLATION
LDOEN
MOSI/A1
MISO/SDA
SCLK/SCL
TX3
RX3
GPIO12
GPIO15
UART3
CTS3
RTS3VEXTV18
TRANSMITTER
SYNC
LOGIC-LEVEL
TRANSLA
TION
CRYSTAL
OSCILLATOR
FRACTIONAL
BAUD-RATE
GENERATOR
SPI/I2C
CS/A0
RST
IRQ
XIN
XOUT
DGNDAGND
MAX14830MAX14830Quad Serial UART with 128-Word FIFOs
Functional Diagram
(Voltages referenced to AGND.)
VL, VA, VEXT, XIN.................................................-0.3V to +4.0V
V18, XOUT.............-0.3V to the lesser of (VA + 0.3V) and +2.0V
RST, IRQ, MOSI/A1, CS/A0, SCLK/SCL,
MISO/SDA, LDOEN, SPI/I2C...................-0.3V to (VL + 0.3V)
TX0, RX0, CTS0, GPIO0, GPIO1,
GPIO2, GPIO3.....................................-0.3V to (VEXT + 0.3V)
TX1, RX1, CTS1, GPIO4, GPIO5,
GPIO6, GPIO7.....................................-0.3V to (VEXT + 0.3V)
TX2, RX2, CTS2, GPIO8, GPIO9,
GPIO10, GPIO11.................................-0.3V to (VEXT + 0.3V)
TX3, RX3, CTS3, GPIO12, GPIO13,
GPIO14, GPIO15.................................-0.3V to (VEXT + 0.3V)
DGND................................................................... -0.3V to +0.3V
Continuous Power Dissipation (TA = +70°C)
TQFN (derate 38.5mW/°C above +70°C)................3076.9mW
Operating Temperature Range............................-40°C to +85°C
Maximum Junction Temperature......................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s)....................................300°C
Soldering Temperature (reflow) ......................................+260°C
TQFN Junction-to-Ambient Thermal Resistance (θJA) ..........26°C/W Junction-to-CaseThermal Resistance (θJC) ..................1°C/W
(Note 1)(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.5V, VL = +1.8V, VEXT = +2.8V, TA = +25°C.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDigital Interface Supply VoltageVL1.713.6V
Analog Supply VoltageVA2.353.6V
UART Interface Logic Supply
VoltageVEXT1.713.6V
Logic Supply VoltageV181.651.95V
CURRENT CONSUMPTIONVA Supply CurrentI A
1.8MHz crystal oscillator active, PLL
disabled, SPI/I2C interface idle, UART
interfaces idle, VLDOEN = VL
400µA
Baud rate = 1Mbps, 20MHz external clock,
SPI/I2C interface idle, PLL disabled, all
UARTs in loopback mode, VLDOEN = 0V
0.5mA
VA Shutdown Supply CurrentIASHDNShutdown mode, VLDOEN = 0V, VRST = 0V,
all inputs and outputs are idle35µA
VL Shutdown or Sleep Supply
CurrentILShutdown mode, VLDOEN = 0V, VRST = 0V,
all inputs and outputs are idle12µA
VEXT Shutdown Supply CurrentIEXTShutdown mode, VLDOEN = 0V, VRST = 0V,
all inputs and outputs are idle8µA
MAX14830Quad Serial UART with 128-Word FIFOs
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
DC Electrical Characteristics
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.5V, VL = +1.8V, VEXT = +2.8V, TA = +25°C.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSV18 Input Power-Supply Current
in Shutdown ModeI18SHDNShutdown mode, VLDOEN = 0V, VRST = 0V,
all inputs and outputs are idle200µA
V18 Input Power-Supply Current I18
Baud rate = 1Mbps, 20MHz external clock,
PLL disabled, all UARTs in loopback mode,
VLDOEN = 0V (Note 4)mA
SCLK/SCL, MISO/SDAMISO/SDA Output Low Voltage in
I2C ModeVOL,I2CILOAD = -3mA, VL > 2V0.4VILOAD = -3mA, VL < 2V0.2 x VL
MISO/SDA Output Low Voltage in
SPI ModeVOL,SPIILOAD = -2mA0.4V
MISO/SDA Output High Voltage
in SPI ModeVOH,SPIILOAD = 2mAVL - 0.4V
Input Low VoltageVILSPI and I2C mode0.3 x VLV
Input High VoltageVIHSPI and I2C mode0.7 x VLV
Input HysteresisVHYSTSPI and I2C mode0.05 x VLV
Input Leakage CurrentIILVIN = 0 to VL, SPI and I2C mode-1+1µA
Input CapacitanceCINSPI and I2C mode5pF
SPI/I2C, CS/A0, MOSI/A1 INPUTSInput Low VoltageVILSPI and I2C mode0.3 x VLV
Input High VoltageVIHSPI and I2C mode0.7 x VLV
Input HysteresisVHYSTSPI and I2C mode50mV
Input Leakage CurrentIILVIN = 0 to VL, SPI and I2C mode-1+1µA
Input CapacitanceCINSPI and I2C mode5pF
IRQ OUTPUT (OPEN DRAIN)Output Low VoltageVOLILOAD = -2mA0.4V
Output Leakage CurrentILKVIRQ = 0 to VL, IRQ is not asserted-1+1µA
LDOEN AND RST INPUTSInput Low VoltageVIL0.3 x VLV
Input High VoltageVIH0.7 x VLV
Input HysteresisVHYST50mV
Input Leakage CurrentIINVIN = 0 to VL-1+1µA
UART INTERFACE
RTS0, RTS1, RTS2, RTS3, TX0, TX1, TX2, TX3 OUTPUTSOutput Low VoltageVOLILOAD = -2mA0.4V
Output High VoltageVOHILOAD = 2mAVEXT - 0.4V
Input Leakage CurrentIINOutput is three-stated, VRTS_ = 0 to VEXT-1+1µA
Input CapacitanceCINHigh-Z mode5pF
MAX14830Quad Serial UART with 128-Word FIFOs
DC Electrical Characteristics (continued)
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.5V, VL = +1.8V, VEXT = +2.8V, TA = +25°C.) (Notes 2, 3)
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25°C.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
RX0, RX1, RX2, RX3, CTS0, CTS1, CTS2, CTS3 INPUTSInput Low VoltageVIL0.3 x VEXTV
Input High VoltageVIH0.7 x VEXTV
Input HysteresisVHYST50mV
CTS0, CTS1, CTS2, CTS3 Input
Leakage CurrentIIN_CTSVCTS_ = 0 to VEXT-1+1µA
RX0, RX1, RX2, RX3 Pullup
Current IIN_RX_VRX_ = 0V, VEXT = 3.6V-7.5-5.5-3.5µA
Input CapacitanceCIN_UART5pF
GPIO0–GPIO15 INPUTS/OUTPUTSOutput Low VoltageVOL
ILOAD = -20mA, VEXT > 2.3V, push-pull
or open drain0.45
ILOAD = -20mA, VEXT < 2.3V, push-pull
or open drain0.55
Output High VoltageVOHILOAD = 5mA, push-pullVEXT - 0.4V
Input Low VoltageVILGPIO_ is conigured as an input0.4V
Input High VoltageVIHGPIO_ is conigured as an input2/3 x VEXTV
Pulldown CurrentIPDGPIO_ = VEXT = 3.6V3.55.57.5µA
XINInput Low VoltageVIL0.2V
Input High VoltageVIH1.2V
Input CapacitanceCXIN16pF
XOUTInput CapacitanceCXOUT16pF
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL OSCILLATORExternal Crystal FrequencyfXOSC14MHz
External Clock FrequencyfCLK0.535MHz
External Clock Duty Cycle(Note 5)4555%
Baud-Rate Generator Clock InputfREF(Note 5)96MHz
MAX14830Quad Serial UART with 128-Word FIFOs
DC Electrical Characteristics (continued)
AC Electrical Characteristics
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25°C.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
I2C BUS: TIMING CHARACTERISTICS (SEE FIGURE 1)SCL Clock FrequencyfSCL
Standard mode100
kHzFast mode400
Fast mode plus1000
Bus Free Time Between a STOP
and START ConditiontBUF
Standard mode4.7Fast mode1.3
Fast mode plus0.5
Hold Time for START Condition
and Repeated START ConditiontHD:STA
Standard mode4.0Fast mode0.6
Fast mode plus0.26
Low Period of the SCL ClocktLOW
Standard mode4.7Fast mode1.3
Fast mode plus0.5
High Period of the SCL ClocktHIGH
Standard mode4.0Fast mode0.6
Fast mode plus0.26
Data Hold TimetHD:DAT
Standard mode00.9Fast mode00.9
Fast mode plus0
Data Setup TimetSU:DAT
Standard mode250Fast mode100
Fast mode plus50
Setup Time for Repeated START
ConditiontSU:STA
Standard mode4.7Fast mode0.6
Fast mode plus0.26
Rise Time of SDA and SCL
Signals Receiving tR
Standard mode (0.3 x VL to 0.7 x VL)
(Note 6)
20 +
0.1Cb1000Fast mode (0.3 x VL to 0.7 x VL) (Note 6)20 +
0.1Cb300
Fast mode plus120
Fall Time of SDA and SCL
Signals tF
Standard mode (0.7 x VL to 0.3 x VL)
(Note 6)
20 +
0.1Cb300Fast mode (0.7 x VL to 0.3 x VL) (Note 6)20 +
0.1Cb300
Fast mode plus120
Setup Time for STOP ConditiontSU:STO
Standard mode4.7Fast mode0.6
Fast mode plus0.26
Capacitive Load for SDA and SCL Cb
Standard mode400Fast mode400
MAX14830Quad Serial UART with 128-Word FIFOs
AC Electrical Characteristics (continued)
Note 2: All devices are production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 3: Currents entering the IC are negative, and currents exiting the IC are positive.
Note 4: When V18 is powered by an external voltage regulator, the external power supply must have current capability above or
equal to I18.
Note 5: Not production tested. Guaranteed by design.
Note 6: Cb is the total capacitance of either the clock or data line of the synchronous bus in pF.(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25°C.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCL and SDA I/O CapacitanceCI/O(Note 5)10pF
Pulse Width of Spike
SuppressedtSP50ns
SPI BUS: TIMING CHARACTERISTICS (SEE FIGURE 2)SCLK Clock PeriodtCH+CL38.4ns
SCLK Pulse Width HightCH16ns
SCLK Pulse Width LowtCL16ns
CS Fall to SCLK Rise TimetCSS0ns
MOSI Hold TimetDH3ns
MOSI Setup TimetDS5ns
Output Data Propagation Delay tDO20ns
MISO Rise and Fall TimestFT10ns
CS Hold TimetCSH30ns
MAX14830Quad Serial UART with 128-Word FIFOs
AC Electrical Characteristics (continued)
Figure 1. I2C Timing Diagram
Figure 2. SPI Timing Diagram
SDA
START CONDITION
(S)
START CONDITION
(S)
REPEATED START CONDITION
(Sr)
STOP CONDITION
(P)
SCL
tHD:STA
tSU:DATtSU:STA
tHD:DATtHD:STAtSU:STOtF
tBUF
tHIGHtLOWtRtF
SCLK
MOSI
MISO
tCSStCL
tDS
tDH
tCH
tDO
tCSH
MAX14830Quad Serial UART with 128-Word FIFOs
Test Circuits/Timing Diagrams
(TA = +25°C, unless otherwise noted.)
GPIO_ OUTPUT LOW VOLTAGE
vs. SINK CURRENT (PUSH-PULL)MAX14830 toc02
VOL (V)
ISINK
(mA)21
VEXT = 3.3V
VEXT = 2.5V
VEXT = 1.8V
TRANSMITTER SYNCHRONIZATIONMAX14830 toc03
200µs/div
TX0
2V/div
138.46kbaud
TX1
2V/div
19.23kbaud
TX2
2V/div
9.615kbaud
TX3
2V/div
6.41kbaud
GPIO_ OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT (PUSH-PULL)MAX14830 toc01
VOH (V)
ISOURCE
(mA)214
VEXT = 3.3V
VEXT = 2.5V
VEXT = 1.8V
MAX14830Quad Serial UART with 128-Word FIFOs
Typical Operating Characteristics
PINNAMEFUNCTIONSPI/I2CSPI or Active-Low I2C Selector Input. Drive SPI/I2C high to enable SPI. Drive SPI/I2C low to enable I2C.LDOENLDO Enable Input. Drive LDOEN high to enable the internal 1.8V LDO. Drive LDOEN low to disable the
internal LDO. When LDOEN is low, V18 can be supplied by an external voltage source.MISO/SDASerial-Data Output. When SPI/I2C is high, MISO/SDA functions as the MISO, SPI serial-data output.
When SPI/I2C is low, MISO/SDA functions as the SDA, I2C serial-data input/output.SCLK/SCLSerial-Clock Input. When SPI/I2C is high, SCLK/SCL functions as the SCLK, SPI serial-clock input (up to
26MHz). When SPI/I2C is low, SCLK/SCL functions as the SCL, I2C serial-clock input (up to 1MHz).CS/A0
Active-Low Chip-Select and Address 0 Input. When SPI/I2C is high, CS/A0 functions as the CS, SPI
active-low chip-select input. When SPI/I2C is low, CS/A0 functions as the A0, I2C device address
programming input. Connect CS/A0 to SDA, SCL, DGND, or VL when SPI/I2C is low.MOSI/A1
Serial-Data and Address 1 Input. When SPI/I2C is high, MOSI/A1 functions as the MOSI, SPI serial-
data input. When SPI/I2C is low, MOSI/A1 functions as the A1, I2C device address programming input.
Connect MOSI/A1 to SDA, SCL, DGND, or VL when SPI/I2C is low.IRQActive-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending.RSTActive-Low Reset Input. Drive RST low to force all of the UARTs into hardware reset mode. In hardware
reset mode, the oscillator and the internal PLL are shut down and there is no clock activity.
TOP VIEW
MAX14830
TQFN
(7mm × 7mm)GPIO2
GPIO3
RX0
TX0
GPIO4
GPIO5
GPIO6
GPIO7
*EP
*CONNECT EP TO AGND.23456789101112
V18
AGND
XIN
XOUT
VEXT
TX3
RX3
CTS3
RTS3
GPIO15
GPIO14
GPIO1GPIO0
DGND
RST
MOSI/A1
SCLK/SCLMISO/SDA
LDOEN3534333231302928272625
RX1TX1GPIO8GPIO9GPIO10GPIO11RX2TX2GPIO12GPIO13
SPI/
I2C
/A0
IRQ
RTS0
CTS0
RTS1
RTS2CTS2
CTS1
MAX14830Quad Serial UART with 128-Word FIFOs
Pin Description
Pin Coniguration
PINNAMEFUNCTIONVL
Digital Interface Logic-Level Supply. VL powers the internal logic-level translators for RST, IRQ, MOSI/
A1, CS/A0, SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C. Bypass VL with a 0.1µF ceramic capacitor to
DGND.DGNDDigital GroundGPIO0
General-Purpose Input/Output 0. GPIO0 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO0 has a weak pulldown resistor to ground. GPIO0 is
the reference clock output when bit 7 of the TxSynch register is set to 1 (see the UART Clock to GPIO
section for more information).GPIO1
General-Purpose Input/Output 1. GPIO1 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO1 has a weak pulldown resistor to ground. GPIO1 is the
TIMER output when bit 7 of the TIMER2 register is set to 1.GPIO2General-Purpose Input/Output 2. GPIO2 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO2 has a weak pulldown resistor to ground. GPIO3General-Purpose Input/Output 3. GPIO3 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO3 has a weak pulldown resistor to ground.RTS0
Active-Low Request-to-Send Output for UART0. RTS0 can be set high or low by programming the LCR
register. RTS0 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is
set to 1.CTS0Active-Low Clear-to-Send Input for UART0. CTS0 is a low control status input.RX0Serial Receiving Data Input for UART0. RX0 has a weak pullup to VEXT.TX0Serial Transmitting Data Output for UART0GPIO4
General-Purpose Input/Output 4. GPIO4 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO4 has a weak pulldown resistor to ground. GPIO4 is
the reference clock output when bit 7 of the TxSynch register is set to 1 (see the UART Clock to GPIO
section for more information).GPIO5
General-Purpose Input/Output 5. GPIO5 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO5 has a weak pulldown resistor to ground. GPIO5 is the
TIMER output when bit 7 of the TIMER2 register is set to 1.GPIO6General-Purpose Input/Output 6. GPIO6 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO6 has a weak pulldown resistor to ground.GPIO7General-Purpose Input/Output 7. GPIO7 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO7 has a weak pulldown resistor to ground.RTS1
Active-Low Request-to-Send Output for UART1. RTS1 can be set high or low by programming the LCR
register. RTS1 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is
set to 1.CTS1Active-Low Clear-to-Send Input for UART1. CTS1 is a low control status input.RX1Serial Receiving Data Input for UART1. RX1 has a weak pullup to VEXT.TX1Serial Transmitting Data Output for UART1GPIO8
General-Purpose Input/Output 8. GPIO8 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO8 has a weak pulldown resistor to ground. GPIO8 is
the reference clock output when bit 7 of the TxSynch register is set to 1 (see the UART Clock to GPIO
section for more information).
MAX14830Quad Serial UART with 128-Word FIFOs
Pin Description (continued)
PINNAMEFUNCTIONGPIO9
General-Purpose Input/Output 9. GPIO9 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO9 has a weak pulldown resistor to ground. GPIO9 is the
TIMER output when bit 7 of the TIMER2 register is set to 1.GPIO10General-Purpose Input/Output 10. GPIO10 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO10 has a weak pulldown resistor to ground.GPIO11General-Purpose Input/Output 11. GPIO11 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO11 has a weak pulldown resistor to ground.RTS2
Active-Low Request-to-Send Output for UART2. RTS2 can be set high or low by programming the LCR
register. RTS2 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is
set to 1.CTS2Active-Low Clear-to-Send Input for UART2. CTS2 is a low control status input.RX2Serial Receiving Data Input for UART2. RX2 has a weak pullup to VEXT.TX2Serial Transmitting Data Output for UART2GPIO12
General-Purpose Input/Output 12. GPIO12 is user-programmable as an input or output (push-pull or
open drain) or external event interrupt source. GPIO12 has a weak pulldown resistor to ground. GPIO12
is the reference clock output when bit 7 of the TxSynch register is set to 1 (see the UART Clock to GPIO
section for more information).GPIO13
General-Purpose Input/Output 13. GPIO13 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO13 has a weak pulldown resistor to ground. GPIO13 is the
TIMER output if bit 7 of the TIMER2 register is set to 1.GPIO14General-Purpose Input/Output 14. GPIO14 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO14 has a weak pulldown resistor to ground.GPIO15General-Purpose Input/Output 15. GPIO15 is user-programmable as an input or output (push-pull or open
drain) or external event interrupt source. GPIO15 has a weak pulldown resistor to ground.RTS3
Active-Low Request-to-Send Output for UART3. RTS3 can be set high or low by programming the LCR
register. RTS3 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is
set to 1.CTS3Active-Low Clear-to-Send Input for UART3. CTS3 is a low control status input.RX3Serial Receiving Data Input for UART3. RX3 has a weak pullup to VEXT.TX3Serial Transmitting Data Output for UART3VEXTTransceiver Interface Level Supply. VEXT powers the internal logic-level translators for RX_, TX_, RTS_,
CTS_, and GPIO_. Bypass VEXT with a 0.1µF ceramic capacitor to DGND.XOUTCrystal Output. When using an external crystal, connect one end of the crystal to XOUT and the other to
XIN. When using an external clock source, leave XOUT unconnected.XINCrystal/Clock Input. When using an external crystal, connect one end of the crystal to XIN and the other
one to XOUT. When using an external clock source, drive XIN with the external clock. AGNDAnalog GroundVAAnalog Supply. VA powers the PLL, and the internal LDO. Bypass VA with a 0.1µF ceramic capacitor to
AGND.V18Internal 1.8V LDO Output and 1.8V Logic Supply Input. Bypass V18 with a 1µF ceramic capacitor to
DGND.EPExposed Paddle. Connect EP to AGND. Do not use EP as the main AGND connection.
MAX14830Quad Serial UART with 128-Word FIFOs
Pin Description (continued)
Detailed DescriptionThe MAX14830 quad UART bridges an SPI/MICROWIRE®
or I2C microprocessor bus to an asynchronous
interface like RS-485, RS-232, or IrDA. The MAX14830
contains advanced UARTs and baud-rate generators with a
synchronous serial-data interface and an interrupt
generator. The MAX14830 is configured by writing an
8-bit word to the configuration registers through either SPI
or I2C. These registers are organized by related function
as shown in the Register Map.
The host controller loads transmit data into the THR
register through SPI or I2C. This data is automatically
pushed into the Transmit FIFOs, formatted, and sent
out at TX_. The MAX14830 adds START and STOP and
parity bits to the data and sends the data out at the
selected baud rates. The clock configuration registers
determine the baud rates, clock source selection, clock
frequency prescaling, and fractional baud-rate generators.
The MAX14830 receiver detects a START bit as a high-to-
low RX_ transition. An internal clock samples this data at
16 times the data rate. The received data is automatically
placed in the Receive FIFOs and can then be read out of
the RxFIFOs through the RHRs.
The MAX14830 features four identical UARTS. Text in this
data sheet references individual UART operation, unless
otherwise noted.
Receive and Transmit FIFOsThe UART’s receiver and the transmitter each have a
128-word deep FIFO reducing the intervals that the host
processor needs to dedicate for high-speed, high-volume
data transfer. As the data rates of the asynchronous RX_
and TX_ interfaces increase and get closer to those of
the host controller’s SPI/I2C data rates, UART manage-
ment and flow control can make up a significant portion
of the host’s activity. By increasing FIFO size, the host is
interrupted less often and can utilize SPI and I2C burst
data block transfers to/from the FIFOs.
FIFO trigger levels can generate interrupts to the host
controller, signaling that programmed FIFO fill levels have
been reached. The transmitter and receiver trigger levels
are programmed through FIFOTrigLvl with a resolution
of eight FIFO locations. When a Receive FIFO trigger is
generated, the host knows that the Receive FIFO has a
defined number of words waiting to be read out or that
a known number of vacant FIFO locations are available,
ready to be filled. The Transmit FIFO trigger generates
an interrupt when the Transmit FIFO level is above the
programmed trigger level. The host then knows to throttle
data writing to the Transmit FIFO.
The host can read out the number of words present in
each of the FIFOs at any time through the TxFIFOLvl and
RxFIFOLvl registers.
Transmitter OperationFigure 3 shows the structure of the transmitter with the
TxFIFO. The Transmit FIFO can hold up to 128 words that
are written to it through the Transmit Hold Register (THR).
The current number of words in the TxFIFO can be read
out through the TxFIFOLvl register The Transmit FIFO
can be programmed to generate an interrupt when a
programmed number of words are present in the TxFIFO
through the FIFOTrgLvl register. The TxFIFO interrupt
trigger level is selectable through FIFOTrgLvl[3:0]. When
the Transmit FIFO fill level reaches the programmed
trigger level, the ISR[4] interrupt is set.
The Transmit FIFO is empty when ISR[5]:TFifoEmptyInt
is set. ISR[5] turns high when the transmitter starts
transmitting the last word in the TxFIFO. Hence the
transmitter is completely empty after ISR[5] is set with an
additional delay equal to the length of a complete character
(including START, parity, and STOP bits).
MICROWIRE is a registered trademark of National
Figure 3. Transmit FIFO Signals
DATA FROM SPI/I2C
INTERFACE
THR128
TRIGGERISR[4]
TxFIFOLvL
FIFO TRGLVL[3:0]
CURRENT FILL LEVEL
TRANSMIT
FIFO
TRANSMIT
SHIFT-REGISTERTX_
LEVEL
EMPTYISR[5]
MAX14830Quad Serial UART with 128-Word FIFOs
The contents of the TxFIFO and RxFIFOs are both
cleared through MODE2[1]: FIFORst. To halt transmis-
sion, set MODE1[1]: TxDisabl to 1. After MODE1[1] is
set, the transmitter completes transmission of the current
character and then ceases transmission.
The TX_ output logic can be inverted through IrDA[5]:
TxInv. If not stated otherwise, all transmitter logic
described in this data sheet assumes that IrDA[5] is 0.
Receiver OperationThe receiver expects the format of the data at RX_ to be
as shown in Figure 4. The quiescent logic state is high
and the first bit (the START bit) is logic-low. The receiver
samples the data near the midbit instant (Figure 4). The
received words and their associated errors are deposited
into the Receive FIFO. Errors and status information are
stored for every received word (Figure 5). The host reads
the data out of the Receive FIFO through the Receive
Hold Register (RHR), oldest data first. The status information
of the most recently read word in the RHR is located in
the Line Status Register (LSR). After a word is read out
of the RHR, the LSR contains the status information for
that word.
The following three error conditions are determined for
each received word: parity error, framing error, and noise
on the line. Line noise is detected by checking the consistency
of the logic of the three samples (Figure 6).
Figure 4. Receive Data Format
Figure 5. Receive FIFO
RECEIVED DATA
LSB
STARTD0D1D2D3D4D5D6D7PARITYSTOPSTOP
MSB
MID BIT
SAMPLING
RX_
BAUD
BLOCK23456789
ONE BIT PERIOD11
MAJORITY
CENTER
SAMPLER13141516
RECEIVE FIFO
FIFOTrgLvl[7:4]TRIGGERISR[3]
WORDERROR128
RxFIFOLvl
TIMEOUT
EMPTY
ERRORS
OVERRUNLSR[1]
RECEIVED
DATA
RHR
RECEIVERRX_
I2C/SPI INTERFACE
LSR[0]
ISR[6]
LSR[5:2]
CURRENT FILL LEVEL
MAX14830Quad Serial UART with 128-Word FIFOs
The receiver can be turned off through MODE1[0]:
RxDisabl. When this bit is set to 1, the MAX14830 turns
the receiver off immediately following the current word
and does not receive any further data. The RX_ input
logic can be inverted through IrDA[4]: RxInv.
Line Noise IndicationWhen operating in standard or 2x (i.e., not 4x) rate mode,
the MAX14830 checks that the binary logic level of the
three samples per received bit are identical. If any of the
three samples have differing logic levels, then noise on
the transmission line has affected the received data and is
considered to be noisy. This noise indication is reflected
in the LSR[5]: RxNoise bit for each received byte. Parity
errors are another indication of noise, but are not as
sensitive.
Clocking and Baud-Rate GenerationThe MAX14830 can be clocked by an external crystal,
or an external clock source. Figure 7 shows a simplified
diagram of the clocking circuitry. When the MAX14830 is
clocked by a crystal, the STSInt[5]: ClockReady indicates
when the clocks have settled and the baud-rate generator
is ready for stable operation.
Each UART baud rate can be individually programmed.
To achieve fast baud rate changes, first disable the
UART’s clock by setting CLKDisabl to 1. Then change
the baud rate divisor and subsequently enable the clock
via CLKDisabl.
To check that the UART’s clocking is programmed as
expected, route the baud rate clock to RTS using the
CLKtoRTS bit. The clock rate of this is 16x the baud rate
in standard operating mode and 8x the baud rate in 2x
rate mode. In 4x rate mode, the CLKOUT frequency is 4x
the programmed baud rate. If the fractional portion of the
baud-rate generator is used, the clock is not regular and
exhibits jitter.
Crystal OscillatorSet BRGConfig[6]: CLKDisabl to 0 and CLKSource[1]:
CrystalEn to 1 to enable and select the crystal oscillator.
The on-chip crystal oscillator circuit has load capaci-
tances of 16pF (typ) integrated in both XIN and XOUT.
Connect an external crystal or ceramic oscillator between
XIN and XOUT.
External Clock SourceConnect an external clock source to XIN when not
using a crystal oscillator. Leave XOUT unconnected. Set
CLKSource[1]: CrystalEn to 0 to select external clocking.
PLL and PredividerThe internal predivider and PLL allow for a wide range of
external clock frequencies and baud rates. The PLL can
be configured to multiply the input clock rate by a factor
of 6, 48, 96, or 144 through the PLLConfig register. The
predivider, located between the input clock and the PLL,
allows division of the input clock by a factor between 1
and 63 by writing to PLLConfig[5:0]. See the PLLConfig
register description for more information.
Figure 7. Clock Selection Diagram
PLLBypassCrystalEn
XOUTCRYSTAL
OSCILLATOR
PLLEnClkDisabl[0...3]
XIN
DIVIDERPLLFRACTIONAL
BAUD RATE
GENERATOR 1
FRACTIONAL
BAUD RATE
GENERATOR 2
FRACTIONAL
BAUD RATE
GENERATOR 3
FRACTIONAL
BAUD RATE
GENERATOR 0
MAX14830Quad Serial UART with 128-Word FIFOs
Fractional Baud-Rate GeneratorsThe internal fractional baud-rate generator provides a
high degree of flexibility and high resolution in baud-
rate programming. The baud-rate generator has a 16-bit
integer divisor and a 4-bit word for the fractional divisor.
The fractional baud-rate generator can be used with the
external crystal or clock source.
The integer and fractional divisors are calculated through
the divisor, D:
REFfD16BaudRate=×
where fREF is the reference frequency input to the baud-
rate generator and D is the ideal divisor. In 2x and 4x rate
modes, replace the divisor 16 by 8 or 4, respectively.
The integer divisor portion, DIV, of the divisor, D, is
obtained by truncating D:
DIV = TRUNC(D)
DIV can be a maximum of 16 bits wide and is programmed
into the 2-byte-wide registers DIVMSB and DIVLSB. The
minimum allowed value for DIVLSB is 1.
The fractional portion of the divisor, FRACT, is a 4-bit nib-
ble, which is programmed into BRGConfig[3:0]. The maxi-
mum value is 15, allowing the divisor to be programmed
with a resolution of 0.0625. FRACT is calculated as:
FRACT = ROUND(16 x (D-DIV)).
The following is an example of calculating the divisor. It is
based on a required baud rate of 190kbaud and a refer-
ence input frequency of 28.23MHz and default rate mode.
The ideal divisor is calculated as:
D = 28,230,000 / (16 x 190,000) = 9.286
hence DIV = 9.
FRACT = ROUND(4.579) = 0x05
so that DIVMSB = 0x00, DIVLSB = 0x09, and
BRGConfig[3:0] = 0x05.
The resulting actual baud rate can be calculated as:
REFACTUAL
ACTUALBR16D=×
For this example: DACTUAL = 9 + 5/16 = 9.313,
where DACTUAL = DIV + (FRACT/16) and
BRACTUAL= 28,230,000/(16 x 9.3125) = 189,463.087
baud
Thus, the baud rate is within 0.28% of the ideal rate.
2x and 4x Rate ModesTo support higher baud rates than possible with standard
(16x sampling) operation, the MAX14830 offers 2x and
4x rate modes. In this case, the reference clock rate only
needs to be either 8x or 4x of the baud rate, respectively.
In 4x mode only, the bits are only sampled once, at the
midbit instant, instead of the usual three samples to
determine the logic value of the bits. This reduces the
tolerance to line noise on the received data. The 2x and
4x modes are selectable through BRGConfig[5:4]. Note
that IrDA encoding and decoding does not operate in 2x
and 4x modes.
When 2x rate mode is selected, the actual baud rate is
twice the rate programmed into the baud-rate generator. If
4x rate mode is enabled, the actual baud rate on the line
is quadruple that of the programmed baud rate (Figure 8).
Figure 8. 2x and 4x Baud Rates
FRACTIONAL
RATE
GENERATOR
DIVLSB
DIVMSB
FRACT
NOTE: IrDA DOES NOT WORK IN 2x AND 4x MODES.
fREF
BRGConfig[5:4]
RATE MODE
SELECTION
1 x BAUD RATE,
2 x BAUD RATE,
4 x BAUD RATE
MAX14830Quad Serial UART with 128-Word FIFOs
Low-Frequency TimerThe general-purpose timer can be used to generate a
low-frequency clock at a GPIO output and can, for exam-
ple, be used to drive external LEDs. The low-frequency
clock is a divided replica of a given UART baud-rate clock.
The timer is internally routed to the GPIO_ outputs when
enabled in the TIMER2 register as follows:UART0: GPIO1UART1: GPIO5UART2: GPIO9UART3: GPIO13
The clock pulses at the GPIOs are generated at a rate
defined by the baud-rate generator and the timer divider
(Figure 9). The baud-rate generator clock is divided
by (1024 x TIMERx), where TIMERx is a 15-bit integer
programmed into the TIMER1 and TIMER2 registers. The
timer output is a 50% duty cycle clock.
UART Clock to GPIOThe MAX14830 reference clock can be routed to the
GPIO0, GPIO4, GPIO8, and/or GPIO12 outputs in case a
synchronous high-frequency clock is needed by another
device. Enable routing a UART clock to GPIO0, GPIO4,
GPIO8, and/or GPIO12 in the TxSynch register. This
output clock could, for example, be used to clock another
UART device (Figure 29).
Multidrop ModeIn Multidrop Mode, also known as 9-bit mode, the word
length is 8 bits and a 9th bit is used for distinguishing
between an address and a data word. Multidrop mode is
enabled through MODE2[6]: MultiDrop. Parity checking is
disabled and an SpclCharInt[5]: MultiDropInt interrupt is
generated when an address (9th bit set) is received.
It is up to the host processor to filter out the data intended
for its address. Alternatively the auto data filtering mode
can be used to automatically filter out the data intended
for the station’s specific 9-bit mode address.
Auto Data Filtering in Multidrop ModeIn multidrop mode, the MAX14830 can be configured
to automatically filter out data that is not meant for its
address. The address is user-definable either by pro-
gramming a register value or a combination of a register
value and GPIO hardware inputs. Use either XOFF2
or XOFF2[7:4] in combination with GPIO_ to define the
address.
Enable multidrop mode by setting MODE2[6]: MultiDrop
to 1 and enable auto data filtering by setting MODE2[4]:
SpecialChr to 1.
When using register bits in combination with GPIO_ to
define the address, the MSB of the address is written to
XOFF2[7:4] register bits, while the LSBs of the address
are defined through the GPIOs. To enable this mode,
set FlowCtrl[2]: GPIAddr, MODE2[4]: SpecialChr, and
MODE2[6]: MultiDrop to 1. GPIO_ are automatically read
when FlowCtrl[2]: GPIAddr is set to 1, and the address is
updated on logic changes at GPIO_.
In the auto data filtering mode, the MAX14830 automati-
cally accepts data that is meant for its address and places
this into the Receive FIFO, while it discards data that is
not meant for its address. The received address word is
not put into the FIFO.
Auto Transceiver Direction ControlIn some half-duplex communication systems the trans-
ceiver’s transmitter must be turned off when data is being
received so as not to load the bus. This is the case in half-
duplex RS-485 communication. Similarly in full-duplex
multidrop communication, like RS-485 or RS-422/V.11,
only one transmitter can be enabled at any one time
and the others must be disabled. The MAX14830 can
automatically enable/disable a transceiver’s transmitter
and/or receiver. This relieves the host processor of this
time-critical task.
The RTS_ output is used to control the transceivers’
transmit enable input and is automatically set high when
the MAX14830’s transmitter starts transmission.
Figure 9. GPIO_ Clock Pulse Generator
UART_
FRACTIONAL
RATE
GENERATOR
fREFTIMERx
GPIO_GPIO_
TmrtoGPIO
DIVIDE-BY-1024
MAX14830Quad Serial UART with 128-Word FIFOs
This occurs as soon as data is present in the Transmit
FIFO. Auto transceiver direction control is enabled
through MODE1[4]: TrnscvCtrl. Figure 10 shows a typical
MAX14830 connection in a RS-485 application.
The RTS_ output can be set high in advance of TX_ trans-
mission by a programmable time period called the setup
time (Figure 11). The setup time is programmed through
HDplxDelay[7:4]. Similarly, the RTS_ signal can be held
high for a programmable period after the transmitter has
completed transmission. The hold time is programmed
through HDplxDelay[3:0].
Transmitter Triggering and SynchronizationThe MAX14830 allows synchronization of transmitters so
that selected UARTs start transmitting data when a trig-
ger command is received. Optional delays can also be
programmed, which delay the start of transmission after a
trigger command is received. A UART’s transmitter can be
assigned one of 16 possible SPI/I2C trigger commands.
A trigger command is defined as any of 16 special values
written into the GloblComnd register (see the GloblComnd
section for more information). When a byte is written
into the GloblComnd register, UART select bits (U0 and
U1) are ignored by the MAX14830, and the GloblComnd
applies to all four UARTs. Transmission is initiated when
the MAX14830 receives the assigned SPI/I2C trigger
command if the selected transmitter is initially disabled
and data has been loaded into its TxFIFO.
Enable and configure transmitter synchronization in the
TxSynch register. Triggering and synchronization requires
that the TxFIFOs are disabled before the trigger is
received. This can be done by setting the MODE1[1] bit
to 1 or by utilizing the auto transmitter disable function
(TxSynch[4] is 1).
Transmitter SynchronizationSynchronize multiple UARTs so their transmitters start
transmission simultaneously by assigning a common trig-
ger command to the UARTs that should be synchronized.
Intrachip and Interchip SynchronizationIntrachip transmitter triggering occurs when any of the
four UARTs in a MAX14830 are triggered by one trigger
command. This type of synchronization is supported in
both SPI and I2C modes, as the trigger commands are
global commands that are received by all four UARTs
simultaneously.
Interchip transmitter triggering occurs when the UARTs in
different MAX14830 devices are synchronized. This type
of synchronization is achievable in SPI mode only. Pull
the CS of all the MAX14830 devices on the bus low during
the SPI master’s write trigger command so that the com-
mands are received by all UARTs on the shared SPI bus.
I2C protocol does not allow simultaneous addressing of
multiple devices.
Delayed TriggeringA delay can be programmed for delaying the start of trans-
mission after the reception of an assigned trigger com-
mand. Set the delay by programming the SynchDelay1
and SynchDelay2 registers.Figure 10. Auto Transceiver Direction Control
TX_DID
RTS_
RX_
Tx FIFO
Rx FIFO
MAX14830TRANSMITTER
AUTO
TRANSCEIVER
CONTROL
RECEIVER
MAX14840ETX_
FIRST CHARACTERLAST CHARACTER
RTS_
SETUP
HOLD
MAX14830Quad Serial UART with 128-Word FIFOs
Trigger AccuracyThe delay between the time when the MAX14830 receives trigger command and the time when the associated
transmitter starts transmission is made up of a fixed,
deterministic portion and a variable, random component.
Both portions of the delay are dependent on the UART’s
clock and baud rates. When the fractional divider is not
used, the intrinsic trigger delay, tTRIG, is bounded by the
following limits:
TRIGBR6BRt1616××≤≤
where BR is the fractional divider output clock period. This
equation is independent on the rate mode. The reference
point is the time when the trigger command is received by
the MAX14830. This occurs on the final (i.e., the 16th) SPI
clock’s low-to-high transition (Figure 12).
When the fractional baud-rate generator is used, the
random portion is larger than one UART clock period.
Synchronization AccuracyWhen synchronizing multiple UART transmitters, the
accuracy of the TX_ transmitter outputs is based on the
triggering delays of each UART (Figure 13). This skew
has a baud-rate dependent component, similar to the
trigger accuracy equation for a single transmitter output.
Calculate the TX_ transmitter output skew using the
following equation:()SFTRIGSKEWBR5BRtmax16×−×≤
where BRS is the fractional divider output clock of the
lower/slower baud-rate UART and BRF is the fractional
divider output clock of the higher/faster baud-rate UART.
Auto Transmitter DisableThe MAX14830 allows automatic disabling of the
transmitter. Enable auto transmitter disabling functional-
ity by setting TxSynch[4] to 1. When auto transmitter
disabling is activated, the MAX14830 disables the speci-
fied transmitter after it completes sending all the data in
its TxFIFO. New data can then be loaded into the TxFIFO. disabled transmitter does not send out data on the
TX_output when data is present in its TxFIFO.
To enable transmission, either clear the TxAutoDis bit
in the TxSynch register or toggle the TxDisabl bit in the
MODE1 register.
Echo SuppressionThe MAX14830 can suppress echoed data, sometimes
found in half-duplex communication (e.g., RS-485 and
IrDA). If the transceiver’s receiver is not turned off
while the transceiver is transmitting, copies (echoes) are
received by the UART. The MAX14830’s receiver can
block the reception of this echoed data by enabling echo
suppression. Set MODE2[7]: EchoSuprs to 1 to enable
echo suppression.
The MAX14830 receiver can block echoes with a long
round trip delay. The transmitter can be configured
to remain enabled after the end of transmission for a
programmable period of time: the hold time delay
(Figure 14). The hold time delay is set by the
HDplxDelay[3:0] register. See the HDplxDelay Register
section for more information.
Figure 12. Single Transmitter Trigger Accuracy
UNCERTAINTY
INTERVAL
tTRIG_MIN
tTRIG_MAX
TX_
SCLK
MAX14830Quad Serial UART with 128-Word FIFOs
Figure 13. Multiple Transmitter Synchronization Accuracy
Figure 14. Echo Suppression Timing
tTX1_MAX
tTRIGSKEW
tTX1_MIN
tTX0_MAX
tTX0_MINTX0
TX1
SCLK
TX_
RX_
DI TO RO PROPAGATION DELAY
HOLD DELAYSTOP
BIT
RTS_
MAX14830Quad Serial UART with 128-Word FIFOs
Echo suppression can operate simultaneously with auto
transceiver direction control (Figure 15).
Auto Hardware Flow ControlThe MAX14830 is capable of automatic hardware (RTS
and CTS) flow control without the need for host proces-
sor intervention. When AutoRTS control is enabled, the
MAX14830 automatically controls the RTS handshake
without the need for host processor intervention. AutoCTS
flow control separately turns the MAX14830’s transmit-
ter on and off based on the CTS_ input. AutoRTS and
AutoCTS flow control are independently enabled through
FlowCtrl[1:0].
AutoRTS ControlAutoRTS flow control ensures that the Receive FIFO does
not overflow by signaling to the far end UART to stop
data transmission. The MAX14830 does this automati-
cally by controlling RTS_. AutoRTS flow control is enabled
through FlowCtrl[0]: AutoRTS. The HALT and RESUME
levels determine the threshold levels at which RTS_ is
asserted and deasserted. HALT and RESUME are pro-
grammed in FlowLvl. With differing HALT and RESUME
levels, hysteresis can be defined for the RTS_ transitions.
When the RxFIFO fill level reaches the HALT level
(FlowLvl[3:0]), the MAX14830 deasserts RTS_. RTS_
remains deasserted until the RxFIFO is emptied and the
number of words falls to the RESUME level.
Interrupts are not generated when the HALT and
RESUME levels are reached. This allows the host
controller to be completely disengaged from RTS flow
control management.
AutoCTS ControlWhen AutoCTS flow control is enabled, the UART auto-
matically starts transmitting data when the CTS_ input is
logic-level low and stops transmitting when CTS_ is logic-
high. This frees the host processor from managing this
timing-critical flow control task. AutoCTS flow control is
enabled through FlowCtrl[1]: AutoCTS. During AutoCTS
flow control, the CTS interrupt works normally. Set the
IRQEn[7]: CTSIntEn to 0 to disable CTS interrupts then
ISR[7]: CTSInt is fixed to logic 0 and the host does not
receive interrupts from CTS_. If CTS_ is set high during
transmission the MAX14830 completes transmission of
the current word and halts transmission afterwards.
Turn the transmitter off by setting MODE1[1] to 1 before
enabling AutoCTS control.
FIFO Interrupt TriggeringReceive and Transmit FIFO fill-dependent interrupts are
generated if FIFO trigger levels are defined. When the
number of words in the FIFOs reach or exceed a trigger
level, as programmed in FIFOTrgLvl, an ISR[3] or ISR[4]
interrupt is generated. There is no relationship between
the trigger levels and the HALT or RESUME levels.
The FIFO trigger level can, for example, be used for a
block data transfer, since it gives the host an indication
when a given block size of data is available for reading in
the Receive FIFO or available for transfer to the Transmit
FIFO.
Auto Software (XON/XOFF) Flow ControlWhen auto software flow control is enabled, the MAX14830
recognizes and/or sends predefined XON/XOFF charac-
ters to control the flow of data across the asynchronous
serial link. Automatic flow works autonomously and does
not involve host intervention, similar to auto hardware
flow control. To reduce the chance of receiving corrupted
data that equals a single-byte XON or XOFF character,
the MAX14830 allows for double wide (16-bit) XON/XOFF
characters. XON and XOFF are programmed into the
XON1, XON2 and XOFF1, XOFF2 registers.
FlowCtrl[7:3] are used for enabling and configuring
auto software flow control. An ISR[1] interrupt is gener-
ated when XON or XOFF are received and details are
found in SpclCharInt. The IRQ can be masked by setting
IRQEn[1]: SpclChrIEn to 0.
Software flow control consists of transmitter control and
receiver overflow control, which can operate indepen-
dently of one another.Figure 15. Half-Duplex with Echo Suppression
LOGICTRANSMITTERTX_DID
RTS_
RX_
ECHO
SUPPRESSION
RECEIVER
Rx FIFO
Tx FIFO
MAX14840EMAX14830MAX14830Quad Serial UART with 128-Word FIFOs
Transmitter Flow ControlWhen auto transmitter control (FlowCtrl[5:4]) is enabled,
the receiver compares all received words with the XOFF
and XON characters. If an XOFF character is received,
the MAX14830 halts its transmitter from sending further
data. The receiver is not affected and continues reception.
Upon receiving XON, the transmitter then restarts sending
data. The received XON and XOFF characters are filtered
out and are not put into the Receive FIFO, as they do not
have significance to the higher layer protocol. An interrupt
is not generated.
Turn the transmitter off (MODE1[1] = 1) before enabling
transmitter control.
Receiver Overlow ControlWhen auto receiver overflow control (FlowCtrl[7:6]) is
enabled, the MAX14830 automatically sends XOFF and
XON control characters to the far end UART to avoid
receiver overflow. XOFF1/XOFF2 is/are sent when the
Receive FIFO fill level reaches the HALT value set in the
FlowLvl register. When the host controller reads data from
the Receive FIFO to a level equal to the RESUME level
programmed into the FlowLvl register, XON1/XON2 is/
are automatically sent to the far end station to signal it to
resume data transmission.
XON1/XOFF1 is transmitted before XON2/XOFF2 when
dual character (XON1 and XON2/XOFF1 and XOFF2)
flow control is enabled.
Power-Up and IRQIRQ has two functions. During normal operation
(MODE1[7] = 1), IRQ operates as a hardware interrupt
output, whereby the IRQ is active when an interrupt is
pending. An IRQ interrupt can only be produced during
normal operation if at least one of the IRQEn interrupt
enable bits are enabled.
During power-up or following a reset, IRQ has a different
function. It is held low until the MAX14830 is ready for
programming following an initialization delay. Once IRQ
goes high, the MAX14830 is ready to be programmed.
The MODE1[7]: IRQSel bit should then be set to enable
normal IRQ interrupt operation.
In polled mode, the DIVLSB register can be polled to
check whether the MAX14830 is ready for operation. If
the controller gets a valid response from DIVLSB, then
the MAX14830 is ready for operation.
Shutdown ModePull RST to DGND to enter shutdown mode. Shutdown
mode is the lowest power consumption mode. In shut-
down mode, all of the MAX14830 circuitry is off. This
includes the SPI/I2C interface, the registers, the FIFOs,
and clocking circuitry. The LDO is on in shutdown mode.
When the RST input is high, the MAX14830 exits shut-
down mode. The chip initialization is completed when the
MAX14830 sets IRQ to logic-high.
The MAX14830 needs to be reprogrammed following a
shutdown.
Interrupt StructureThe structure of the interrupt is shown in Figure 16.
There are four interrupt source registers for each UART:
ISR, LSR, STSInt, and SpclCharInt. Read the GlobalIRQ 6543
LSR1076543
STSInt10000
GlobalIRQ6543
ISR1076543
ISR
LOW-LEVEL INTERRUPTS
TOP-LEVEL
INTERRUPTS21076543
ISR1076543
ISR106543
SpclCharInt10
IRQ3
IRQ
MODE1[7]:IRQSEL
IRQ1IRQ0IRQ2888
[4]
POWER-UP
COMPLETED
[0]
MAX14830Quad Serial UART with 128-Word FIFOs
register to determine which UART is the source of the
interrupt. The interrupt sources are divided into top-level
and low-level interrupts. The top-level interrupts typically
occur more often and can be read out directly through the
ISR. The low-level interrupts typically occur less often and
their specific source can be read out through the LSR,
STSInt, or SpclChar registers. The three LSBs of the ISR
point to the low-level interrupt registers that contain the
detail of the interrupt source.
Interrupt EnablingEvery interrupt bit of the four interrupt registers can
be enabled or masked through an associated interrupt
enable register bit. These are the IRQEn, LSRIntEn,
SpclChrIntEn, and STSIntEn registers.
Interrupt ClearingWhen an ISR interrupt is pending (i.e. any bit in ISR is
set) and the ISR is subsequently read, the ISR bits and
IRQ are cleared. Both the SpclCharInt and the STSInt
registers are also clear on read (COR). The LSR bits are
only cleared when the source of the interrupt is removed,
not when LSR is read.
Reading the GlobalIRQ register does not clear the IRQ
interrupt.
(All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.)
REGISTERADDRBIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT0
FIFO DATARHR†0x00RData7RData6RData5RData4RData3RData2RData1RData0
THR†0x00TData7TData6TData5TData4TData3TData2TData1TData0
INTERRUPTSIRQEn0x01CTSIEnRFifoEmtyIEnTFifoEmtyIEnTFifoTrgIEnRFifoTrgIEnSTSIEnSpclChrIEnLSRErrIEn
ISR*†0x02CTSIntRFifoEmptyIntTFifoEmptyIntTFifoTrigIntRFifoTrigIntSTSIntSpCharIntLSRErrInt
LSRIntEn0x03——RxNoiseIntEnRBreakIEnFrameErrIEnParityIEnROverrIEnRTimoutIEn
LSR*†0x04CTSbit—RxNoiseRxBreakFrameErrRxParityErrRxOverrunRTimeout
SpclChrIntEn0x05——MltDrpIntEnBREAKIntEnXOFF2IntEnXOFF1IntEnXON2IntEnXON1IntEn
SpclCharInt†0x06——MultiDropIntBREAKIntXOFF2IntXOFF1IntXON2IntXON1Int
STSIntEn¥0x07——ClockRdyIntEn—GPI3IntEnGPI2IntEnGPI1IntEnGPI0IntEn
STSInt†¥0x08——ClockReady—GPI3IntGPI2IntGPI1IntGPI0Int
UART MODESMODE10x09IRQSel——TrnscvCtrlRTSHiZTXHiZTxDisablRxDisabl
MODE20x0AEchoSuprsMultiDropLoopBackSpecialChrRxEmtyInvRxTrgInvFIFORstRST
LCR*0x0BRTSbitTxBreakForceParityEvenParityParityEnStopBitsLength1Length0
RxTimeOut0x0CTimOut7TimOut6TimOut5TimOut4TimOut3TimOut2TimOut1TimOut0
HDplxDelay0x0DSetup3Setup2Setup1Setup0Hold3Hold2Hold1Hold0
IrDA0x0E——TxInvRxInvMIRRTSInvertSIRIrDAEn
FIFOs CONTROLFlowLvl0x0FResume3Resume2Resume1Resume0Halt3Halt2Halt1Halt0
FIFOTrgLvl*0x10RxTrig3RxTrig2RxTrig1RxTrig0TxTrig3TxTrig2TxTrig1TxTrig0
TxFIFOLvl†0x11TxFL7TxFL6TxFL5TxFL4TxFL3TxFL2TxFL1TxFL0
RxFIFOLvl†0x12RxFL7RxFL6RxFL5RxFL4RxFL3RxFL2RxFL1RxFL0
FLOW CONTROLFlowCtrl0x13SwFlow3SwFlow2SwFlow1SwFlow0SwFlowEnGPIAddrAutoCTSAutoRTS
XON10x14Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
XON20x15Bit7Bi6Bit5Bit4Bit3Bit2Bit1Bit0
XOFF10x16Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
MAX14830Quad Serial UART with 128-Word FIFOs
Register Map
*Denotes nonzero default reset value: ISR = 0x60, LCR = 0x05, FIFOTrgLvl = 0xFF, PLLConfig = 0x01, DIVLSB = 0x01,
CLKSource = 0x08, REVID = 0xB4.
†Denotes nonread/write value: RHR = R, THR = W, ISR = COR, SpclCharInt = COR, STSInt = R/COR,
LSR = R, TxFIFOLvl = R, RxFIFOLvl = R, REVID = R.
¥Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7, UART2:
GPIO8–GPIO11, UART3: GPIO12–GPIO15.
‡This register can only be programmed by accessing UART0.
#This register can only be directly addressed in I2C mode. Use extended addressing when operating in SPI mode.
REGISTERADDRBIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT0
GPIOsGPIOConfg¥0x18GP3ODGP2ODGP1ODGP0ODGP3OutGP2OutGP1OutGP0Out
GPIOData¥0x19GPI3DatGPI2DatGPI1DatGPI0DatGPO3DatGPO2DatGPO1DatGPO0Dat
CLOCK CONFIGURATIONPLLConig*‡0x1APLLFactor1PLLFactor0PreDiv5PreDiv4PreDiv3PreDiv2PreDiv1PreDiv0
BRGConig0x1B—CLKDisabl4xMode2xModeFRACT3FRACT2FRACT1FRACT0
DIVLSB0x1CDiv7Div6Div5Div4Div3Div2Div1Div0
DIVMSB0x1DDiv15Div14Div13Div12Div11Div10Div9Div8
CLKSource*‡0x1ECLKtoRTS———PLLBypassPLLEnCystalEn—
GLOBAL REGISTERSGlobalRQ0x1F0000IRQ3IRQ2IRQ1IRQ0
GloblComnd0x1FGlbCom7GlbCom6GlbCom5GlbCom4GlbCom3GlbCom2GlbCom1GlbCom0
SYNCHRONIZATION REGISTERSTxSynch#0x20CLKtoGPIOTxAutoDisTrigDelaySynchEnTrigSel3TrigSel2TrigSel1TrigSel0
SynchDelay1#0x21SDelay7SDelay6SDelay5SDelay4SDelay3SDelay2SDelay1SDelay0
SynchDelay2#0x22SDelay15SDelay14SDelay13SDelay12SDelay11SDelay10SDelay9SDelay8
TIMER REGISTERSTIMER1#0x23Timer7Timer6Timer5Timer4Timer3Timer2Timer1Timer0
TIMER2#0x24TmrToGPIOTimer14Timer13Timer12Timer11Timer10Timer9Timer8
REVISIONREVID*†#0x2510110100
MAX14830Quad Serial UART with 128-Word FIFOs
Register Map (continued)
Detailed Register DescriptionsThe MAX14830 has registers that are 8 bits wide.
Bits 7–0: RData[n]The RHR is the bottom of the Receive FIFO and is the register used for reading data out of the Receive FIFO. It contains
the oldest (first received) character in the Receive FIFO. RHR[0] is the first data bit of the serial-data word received by
the receiver at the RX pin.
RHR—Receive Hold Register
THR—Transmit Hold Register
Bits 7–0: TData[n]The THR is the register that the host controller writes data to for subsequent UART transmission. This data is deposited
in the Transmit FIFO. THR[0] is the LSB. It is the first data bit of the serial-data word that the transmitter sends out, right
after the START bit.
ADDRESS:0x00
MODE:R
BIT76543210
NAMERData7RData6RData5RData4RData3RData2RData1RData0
RESETXXXXXXXX
ADDRESS:0x00
MODE:W
BIT76543210
NAMETData7TData6TData5TData4TData3TData 2TData1TData0
MAX14830Quad Serial UART with 128-Word FIFOs
IRQEn—IRQ Enable RegisterThe IRQEn register is used to enable the IRQ physical interrupt. Any of the eight ISR interrupt sources can be enabled
to generate an IRQ. The IRQEn bits only influence the IRQ output and do not have any effect on the ISR contents or
behavior. Every one of the IRQEn bits operates on an ISR bit.
Note that an error can occur in the TxFIFO when a character is written into THR at the same time as the transmitter is
transmitting out data via TX. In the event of this error condition, the result is that a character will not be transmitted.
In order to avoid this, stop the transmitter when writing data to the THR. This can be done via the TxDisable bit in the
MODE1 register.
Bit 7: CTSIEnThe CTSIEn bit enables IRQ interrupt generation when the CTSInt interrupt bit is set in the ISR. Set the CTSIEn bit low
to disable IRQ generation from CTSInt.
Bit 6: RFifoEmtyIEnThe RFifoEmtyIEn bit enables IRQ interrupt generation when the RFifoEmptyInt interrupt bit is set in the ISR. Set the
RFifoEmtyIEn bit low to disable IRQ generation from RFifoEmptyInt.
Bit 5: TFifoEmtyIEnThe TFifoEmtyIEn bit enables IRQ interrupt generation when the TFifoEmptyInt interrupt bit is set in the ISR. Set the
TFifoEmtyIEn bit low to disable IRQ generation from TFifoEmptyInt.
Bit 4: TFifoTrgIEnThe TFifoTrgIEn bit enables IRQ interrupt generation when the TFifoTrigInt interrupt bit is set in the ISR. Set TFifoTrgIEn
bit low to disable IRQ generation from TFifoTrigInt.
Bit 3: RFifoTrgIEnThe RFifoTrgIEn bit enables IRQ interrupt generation when the RFifoTrigInt interrupt bit is set in the ISR. Set the
RFifoTrgIEn bit low to disable IRQ generation from RFifoTrigInt.
Bit 2: STSIEnThe STSIEn bit enables IRQ interrupt generation when the STSInt interrupt bit is set in the ISR. Set the STSIEn bit low
to disable IRQ generation from STSInt.
Bit 1: SpclChrIEnThe SpclChrIEn bit enables IRQ interrupt generation when the SpCharInt interrupt bit is set in the ISR. Set the SpclChrIEn
bit low to disable IRQ generation from SpCharInt.
Bit 0: LSRErrIEnThe LSRErrIEn bit enables IRQ interrupt generation when the LSRErrInt interrupt bit is set in the ISR[0]. Set the
LSRErrIEn low to disable IRQ generation from LSRErrInt.
ADDRESS:0x01
MODE:R/W
BIT76543210
NAMECTSIEnRFifoEmtyIEnTFifoEmtyIEnTFifoTrgIEnRFifoTrgIEnSTSIEnSpclChrIEnLSRErrIEn
RESET00000000
MAX14830Quad Serial UART with 128-Word FIFOs
ISR—Interrupt Status RegisterThe Interrupt Status Register provides an overview of all interrupts generated in the MAX14830. These interrupts are
cleared upon reading the ISR. When the MAX14830 is operated in polled mode, the ISR can be polled to establish
the UART’s status. In interrupt-driven mode, IRQ interrupts are enabled through the appropriate IRQEn bits. The ISR
contents give direct information on the cause for the interrupt or point to other registers that contain more detailed
information.
Bit 7: CTSIntThe CTSInt is set when a logic state transition occurs at the CTS_ input. This bit is cleared after ISR is read. The current
logic state of the CTS_ input can be read out through LSR[7]: CTS bit.
Bit 6: RFifoEmptyIntThe RFifoEmptyInt is set when the Receive FIFO is empty. This bit is cleared after ISR is read. Its meaning can be
inverted by setting the MODE2[3]: RxEmtyInt bit.
Bit 5: TFifoEmptyIntThe TFifoEmptyInt bit is set when the Transmit FIFO is empty. This bit is cleared once ISR is read.
Bit 4: TFifoTrigIntThe TFifoTrigInt bit is set when the number of characters in the Transmit FIFO is equal to or greater than the Transmit
FIFO trigger level defined in FIFOTrigLvl[3:0]. TFifoTrigInt is cleared when the Transmit FIFO level falls below the trigger
level or after the ISR is read. It can be used as a warning that the Transmit FIFO is nearing overflow.
Bit 3: RFifoTrigIntThe RFifoTrigInt bit is set when the Receive FIFO fill level reaches the Receive FIFO trigger level, as defined in
FIFOTrigLvl[7:4]. This can be used as an indication that the Receive FIFO is nearing overrun. It can also be used to
report that a known number of words are available that can be read out in one block. The meaning of RFifoTrigInt can
be inverted through MODE2[2]. RFifoTrigInt is cleared when ISR is read.
Bit 2: STSIntThe STSInt bit is set high when any bit in the STSInt register that is enabled through a STSIntEn bit is high. The STSInt
bit is cleared upon reading ISR.
Bit 1: SpCharIntThe SpCharInt bit is set high when a special character is received, a line BREAK is detected or an address character is
received in multidrop mode. The cause for the SpCharInt interrupt can be read from the SpclCharInt register, if enabled
through the SpclChrIntEn bits. The SpCharInt interrupt is cleared when the ISR is read.
Bit 0: LSRErrIntThe LSRErrInt bit is set high when any LSR bits, which are enabled through the LSRIntEn, are set. This bit is cleared
after the ISR is read.
ADDRESS:0x02
MODE:COR
BIT76543210
NAMECTSIntRFifoEmptyIntTFifoEmptyIntTFifoTrigIntRFifoTrigIntSTSIntSpCharIntLSRErrInt
RESET01100000
MAX14830Quad Serial UART with 128-Word FIFOs
LSRIntEn—Line Status Interrupt Enable RegisterThe LSR Interrupt Enable register allows routing of LSR interrupt bits to the ISR[0].
Bits 7, 6: No Function
Bit 5: NoiseIntEnSet the NoiseIntEn bit high to enable routing the RxNoise interrupt to LSR[0]. If NoiseIntEn is set low, RxNoise is not
routed to LSR[0].
Bit 4: RBreakIEnSet the RBreakIEn bit high to enable routing the RxBreak interrupt to LSR[0]. If RBreakIEn is set low, RxBreak is not
routed to LSR[0].
Bit 3: FrameErrIEnSet the FrameErrIEn bit high to enable routing the FrameErr interrupt to LSR[0]. If FrameErrIEn is set low, FrameErr is
not routed to LSR[0].
Bit 2: ParityIEnSet the ParityIEn bit high to enable routing the RxParityErr interrupt to LSR[0]. If ParityIEn is set low, RxParityErr is not
routed to the LSR[0].
Bit 1: ROverrIEnSet the ROverrIEn bit high to enable routing the RxOverrun interrupt to LSR[0]. If ROverrIEn is set low, RxOverrun is not
routed to LSR[0].
Bit 0: RTimoutIEnSet the RTimoutIEn bit high to enable routing the RTimeout interrupt to LSR[0]. If RTimoutIEn is set low, the RTimeout
is not routed to LSR[0].
ADDRESS:0x03
MODE:R/W
BIT76543210
NAME——NoiseIntEnRBreakIEnFrameErrIEnParityIEnROverrIEnRTimoutIEn
RESET00000000
MAX14830Quad Serial UART with 128-Word FIFOs
LSR—Line Status RegisterThe Line Status Register shows all errors related to the word in the RxFIFO most recently read out of the RHR. The LSR
bits are not cleared upon a read; these bits stay set until the next character without errors is read out of the RHR. The
LSR also reflects the current state of the CTS_ input.
Bit 7: CTSbitThe CTSbit reflects the current logic state of the CTS_ input. This bit is cleared when the CTS_ input is low. Following a
power-up or reset, the logic state of CTSbit depends on the input of the CTS_ input.
Bit 6: No Function
Bit 5: RxNoiseIf noise is detected on the RX_ input during reception of a character, the RxNoise bit is set for that character. The RxNoise
bit indicates that there was noise on the line while the most recently read character residing in the RHR was being
received. The RxNoise flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[5].
Bit 4: RxBreakIf a line BREAK (RX_ input low for a period longer than the programmed character duration) is detected, a BREAK
character is put in the RxFIFO and the RxBreak bit is set for this character. A BREAK character is represented by
an all-zeros data character. The RxBreak bit distinguishes a regular character with all zeros from a BREAK charac-
ter. LSR[4] corresponds to the character most recently read out of the RHR. RxBreak is cleared after the character
following the BREAK character is read out of the RHR. The RxBreak flag can generate an ISR[0] interrupt if enabled
through LSRIntEn[4].
Bit 3: FrameErrThe FrameErr bit is set high when the received data frame does not match the expected frame format in length. LSR[3]
corresponds to the frame error of the character most recently read out of the RHR. A frame error is related to errors in
expected STOP bits. The FrameErr flag can generate an ISR[0] interrupt, if enabled, through LSRIntEn[3].
Bit 2: RxParityErrIf the parity computed on the character being received does not match the received character’s parity bit, the RxParityErr
bit is set for that character. LSR[2] indicates a parity error for the character most recently read out of the RHR. In 9-bit
multidrop mode (MODE2[6] = 1) the receiver does not check parity and the LSR[2] represents the 9th (i.e. address or
data) bit.
The RxParityErr flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[2].
Bit 1: RxOverrunIf the Receive FIFO is full and additional data is received that does not fit into the Receive FIFO, the LSR[1] bit is set. The
Receive FIFO retains the data in it and discards all new data that does not fit into it. The RxOverrun flag can generate
an ISR[0] interrupt, if enabled through LSRIntEn[1].
ADDRESS:0x04
MODE:R
BIT76543210
NAMECTSbit—RxNoiseRxBreakFrameErrRxParityErrRxOverrunRTimeout
RESETX0000000
MAX14830Quad Serial UART with 128-Word FIFOs
