MAX17000ETG+ ,Complete DDR2 and DDR3 Power-Management SolutionApplications7 PGND2Notebook Computers SHDN 24DDR, DDR2, and DDR3 Memory Supplies 1 2 3 45 6SSTL Mem ..
MAX17003ETJ+ ,High-Efficiency, Quad Output, Main Power-Supply Controllers for Notebook ComputersApplications28 13 CSL5CSL3Main Power Supplies MAX17003CSH3 29 12 CSH5MAX170042 to 4 Li+ Cell Batter ..
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MAX17004ETJ+ ,High-Efficiency, Quad Output, Main Power-Supply Controllers for Notebook ComputersELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ..
MAX17004ETJ+TG38 ,High-Efficiency, Quad Output, Main Power-Supply Controllers for Notebook ComputersMAX17003/MAX1700419-0765; Rev 0; 3/07High-Efficiency, Quad-Output, Main Power-Supply Controllers fo ..
MAX17005AETP+ ,1.2MHz Low-Cost, High-Performance ChargersFeaturesThe MAX17005A/MAX17006A/MAX17015A are high-fre-♦ High Switching Frequency (1.2MHz)quency mu ..
MAX4509CPE ,Fault-Protected, High-Voltage Single 8-to-1/Dual 4-to-1 MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, V =+2.4V, V = +0.8V, V = +2.4V, T = ..
MAX4509CSE ,Fault-Protected, High-Voltage Single 8-to-1/Dual 4-to-1 MultiplexersMAX4508/MAX450919-1414; Rev 0; 1/99Fault-Protected, High-Voltage Single 8-to-1/Dual 4-to-1 Multiple ..
MAX4509CSE+ ,Fault-Protected, High-Voltage Single 8-to-1/Dual 4-to-1 Multiplexers with Output ClampsELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, V =+2.4V, V = +0.8V, V = +2.4V, T = ..
MAX4509ESE ,Fault-Protected, High-Voltage Single 8-to-1/Dual 4-to-1 MultiplexersApplicationsOrdering InformationData-Acquisition Systems PART TEMP. RANGE PIN-PACKAGEIndustrial and ..
MAX4509ESE ,Fault-Protected, High-Voltage Single 8-to-1/Dual 4-to-1 MultiplexersMAX4508/MAX450919-1414; Rev 0; 1/99Fault-Protected, High-Voltage Single 8-to-1/Dual 4-to-1 Multiple ..
MAX4509ESE+ ,Fault-Protected, High-Voltage Single 8-to-1/Dual 4-to-1 Multiplexers with Output ClampsApplications Ordering InformationData-Acquisition Systems TEMP PIN- PKGPARTRANGE PACKAGE CODEIndust ..
MAX17000ETG+
Complete DDR2 and DDR3 Power-Management Solution
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management SolutionEVALUATION KIT AVAILABLE
General DescriptionThe MAX17000 pulse-width modulation (PWM) con-
troller provides a complete power solution for notebook
DDR, DDR2, and DDR3 memory. It comprises a step-
down controller, a source/sink LDO regulator, and a ref-
erence buffer to generate the required VDDQ, VTT, and
VTTR rails.
The VDDQ rail is supplied by a step-down converter
using Maxim’s proprietary Quick-PWM™ controller. The
high-efficiency, constant-on-time PWM controller han-
dles wide input/output voltage ratios (low duty-cycle
applications) with ease and provides 100ns response
to load transients while maintaining a relatively constant
switching frequency. The Quick-PWM architecture cir-
cumvents the poor load-transient timing problems of
fixed-frequency current-mode PWMs while also avoid-
ing the problems caused by widely varying switching
frequencies in conventional constant-on-time and con-
stant-off-time PWM schemes. The controller senses the
current to achieve an accurate valley current-limit pro-
tection. It is also built in with overvoltage, undervoltage,
and thermal protections. The MAX17000 can be set to
run in three different modes: power-efficient SKIP
mode, low-noise forced-PWM mode, and standby
mode to support memory in notebook computer stand-
by operation. The switching frequency is programma-
ble from 200kHz to 600kHz to allow small components
and high efficiency. The VDDQ output voltage can be
set to a preset 1.8V or 1.5V, or be adjusted from 1.0V to
2.5V by an external resistor-divider. This output has 1%
accuracy over line-and-load operating range.
The MAX17000 includes a ±2A source/sink LDO regu-
lator for the memory termination VTT rail. This VTT regu-
lator has a ±5mV deadband that either sources or
sinks, ideal for the fast-changing load burst present in
memory termination applications. This feature also
reduces output capacitance requirements.
The VTTR reference buffer sources and sinks ±3mA,
providing the reference voltage needed by the memory
controller and devices on the memory bus.
The MAX17000 is available in a 24-pin, 4mm x 4mm,
TQFN package.
ApplicationsNotebook Computers
DDR, DDR2, and DDR3 Memory Supplies
SSTL Memory Supplies
FeaturesSMPS Regulator (VDDQ)
Quick-PWM with 100ns Load-Step Response
Output Voltages—Preset 1.8V, 1.5V, or
Adjustable 1.0V to 2.5V
1% VOUTAccuracy Over Line and Load
26V Maximum Input Voltage Rating
Accurate Valley Current-Limit Protection
200kHz to 600kHz Switching FrequencySource/Sink Linear Regulator (VTT)
±2A Peak Source/Sink
Low-Output Capacitance Requirement
Output Voltages-Preset VDDQ/2 or REFIN
Adjustable from 0.5V to 1.5VLow Quiescent Current Standby StateSoft-Start/Soft-ShutdownSMPS Power-Good Window ComparatorVTT Power-Good Window ComparatorSelectable Overvoltage ProtectionUndervoltage/Thermal Protections±3mA Reference Buffer (VTTR)PGOOD1
VTTSVTTR
OVP
BSTDHTONDLCSH2
SKIP618161413
VCC
SHDN
REFIN
VTTI
VTT
PGND2
MAX17000ETG+
PGOOD2
AGND11FBPGND112CSLVDD
TQFN
4mm x 4mmTOP VIEW
STDBY
Pin ConfigurationQuick-PWM is a trademark of Maxim Integrated Products, Inc.
Ordering Information+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PARTTEMP RANGEPIN-PACKAGEMAX17000ETG+ -40°C to +85°C 24 TQFN-EP*
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VIN= 12V, VCC = VDD = VSHDN= VREFIN= 5V, VCSL= 1.8V, STDBY= SKIP= AGND, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
TON to PGND1.......................................................-0.3V to +28V
VDDto PGND1..........................................................-0.3V to +6V
VCCto VDD............................................................-0.3V to +0.3V
OVP to AGND...........................................................-0.3V to +6V
SHDN, STDBY, SKIPto AGND.................................-0.3V to +6V
REFIN, FB, PGOOD1,
PGOOD2 to AGND................................-0.3V to (VCC+ 0.3V)
CSH, CSL to AGND....................................-0.3V to (VCC+ 0.3V)
DL to PGND1..............................................-0.3V to (VDD+ 0.3V)
BST to PGND1...........................................................-1V to +34V
BST to LX..................................................................-0.3V to +6V
DH to LX....................................................-0.3V to (VBST+ 0.3V)
BST to VDD.............................................................-0.3V to +28V
VTTI to PGND2.........................................................-0.3V to +6V
VTT to PGND2............................................-0.3V to (VTTI+ 0.3V)
VTTS to AGND............................................-0.3V to (VCC+ 0.3V)
VTTR to AGND..........................................-0.3V to (VCSL+ 0.3V)
PGND1, PGND2 to AGND.....................................-0.3V to +0.3V
Continuous Power Dissipation (TA= +70°C)
24-Pin, 4mm x 4mm TQFN-EP
(derated 27.8mW/°C above +70°C)..........................2222mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PWM CONTROLLERVIN3 26 Input Voltage Range VCC, VDD 4.5 5.5 V
FB = AGND 1.485 1.500 1.515
FB = VCC 1.782 1.800 1.818 Output Voltage Accuracy VCSL VIN = 4.5V to 26V,
SKIP = VCC
FB = Adj 0.99 1.000 1.01
Output Voltage Range VCSL 1 2.7 V
Load Regulation Error VCSH - VCSL = 0 to 18mV, SKIP = VCC 0.1 %
Line Regulation Error VDD = 4.5V to 5.5V, VIN = 4.5V to 26V 0.25 %
Soft-Start Ramp Time tSSTART Rising edge of SHDN 1.4 2.1 ms
Soft-Stop Ramp Time tSSTOP Falling edge of SHDN 2.8 ms
Soft-Stop Threshold 25 mV
RTON = 96.75k
(600kHz), 167ns nominal -15 +15
RTON = 200k (300kHz),
333ns nominal -10 +10 On-Time Accuracy (Note 2) tONVIN= 12V,
VCSL= 1.2V
RTON = 303.25k
(200kHz), 500ns nominal -15 +15
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMinimum Off-Time tOFF(MIN) (Note 2) 250 350 ns
Quiescent Supply Current (VDD) IDD FB forced above 1.0V, STDBY = AGND or
VCC, TA = +25°C 0.01 1.00 μA
FB forced above 1.0V (SMPS, VTT, and
VTTR blocks); STDBY = VCC 2 4 mA
Quiescent Supply Current (VCC) ICC
FB forced above 1.0V (ultra-skip and VTTR
blocks); STDBY = AGND 275 475 μA
Shutdown Supply Current
(VDD + VCC)ICC + IDDSHDN = AGND, TA = +25°C 0.01 5 μA
TON Pin Shutdown Current ITON SHDN = AGND, VIN = 26V, VDD = 0 or 5V,
TA = +25°C 0.01 1.00 μA
LINEAR REGULATOR (VTT)VTTI Input Voltage Range VTTI 1.0 2.8 V
VTTI Supply Current IVTTI VVTTI = 2.5V, VREFIN = 1.4V 10 50 μA
VTTI Shutdown Current SHDN = AGND, TA = +25°C 10 μA
REFIN Input Bias Current VVTTI = 2.5V, VREFIN = 1.4V -50 +50 nA
REFIN Range VREFIN 0.5 1.5 V
REFIN Disable Threshold VCC -
0.3 V
High-side on-resistance
(source, IVTT = 0.1A) 0.12 0.25 VTT Internal MOSFET
Low-side on-resistance (sink, IVTT = 0.1A) 0.18 0.36
VREFIN = 1V,
IVTT = +50μA -5 +5
VTT Output-Accuracy
Source Load
(VREFIN - 5mV) or
(VCSL/2 - 5mV) to
VTTS, VTT = VTTS VREFIN = 0.5V to 1.5V,
IVTT = +300mA -5
mV
VREFIN = 1V,
IVTT = -50μA -5 +5
VTT Output-Accuracy
Sink Load
(VREFIN + 5mV) or
(VCSL/2 + 5mV) to
VTTS, VTT = VTTS VREFIN = 0.5V to 1.5V,
IVTT = -300mA +5
mV
VTT Load Regulation -50μA to -1A IVTT +50μA to +1A 13 17 mV/A
VTT Line Regulation 1.0V VTTI 2.8V, IVTT = ±100mA 1 mV
Source 2 4 VTT Current Limit Sink -4 -2 A
VTT Current-Limit Soft-Start Time With respect to internal VTT_EN signal 160 μs
VTT Discharge MOSFET OVP = VCC 16
VTTS Input Current TA = +25°C 0.1 1.0 μA
ELECTRICAL CHARACTERISTICS (continued)(VIN= 12V, VCC = VDD = VSHDN= VREFIN= 5V, VCSL= 1.8V, STDBY= SKIP= AGND, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.) (Note 1)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ELECTRICAL CHARACTERISTICS (continued)(VIN= 12V, VCC = VDD = VSHDN= VREFIN= 5V, VCSL= 1.8V, STDBY= SKIP= AGND, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
REFERENCE BUFFER (VTTR)IVTT = ±1mA -10 +10 VTTR Output Accuracy (Adj) REFIN to VTTR IVTT = ±3mA -20 +20
IVTT = ±1mA -10 +10 VTTR Output Accuracy (Preset) VCSL/2 to VTTR IVTT = ±3mA -20 +20
mV
VTTR Maximum
Recommended Current Source/sink 5 mA
FAULT DETECTION (SMPS)SMPS OVP and PGOOD1
Upper Trip Threshold 12 15 18 %
SMPS OVP and PGOOD1
Upper Trip Threshold
Fault-Propagation Delay
tOVP FB forced 25mV above trip threshold 10 μs
SMPS Output Undervoltage
Fault-Propagation Delay tUVP 200 μs
SMPS PGOOD1 Lower Trip
Threshold Measured at FB, hysteresis = 25mV -12 -15 -18 %
PGOOD1 Lower Trip Threshold
Propagation Delay tPGOOD1 FB forced 50mV below PGOOD1 trip
threshold 10 μs
PGOOD1 Output Low Voltage ISINK = 3mA 0.4 V
PGOOD1 Leakage Current IPGOOD1 FB = 1V (PGOOD1 high impedance),
PGOOD1 forced to 5V, TA = +25°C 1 μA
TON POR Threshold VPOR(IN) Rising edge, PWM disabled below this level;
hysteresis = 200mV 3.0 V
FAULT DETECTION (VTT)PGOOD2 Upper Trip Threshold Hysteresis = 25mV 8 10 13 %
PGOOD2 Lower Trip Threshold Hysteresis = 25mV -13 -10 -8 %
PGOOD2 Propagation Delay tPGOOD2 VTTS forced 50mV beyond PGOOD2
trip threshold 10 μs
PGOOD2 Fault Latch Delay VTTS forced 50mV beyond PGOOD2
trip threshold 5 ms
PGOOD2 Output Low Voltage ISINK = 3mA 0.4 V
PGOOD2 Leakage Current IPGOOD2 VTTS = VREFIN (PGOOD2 high impedance),
PGOOD2 forced to 5V, TA = +25°C 1 μA
FAULT DETECTIONThermal-Shutdown Threshold TSHDN Hysteresis = 15°C 160 °C
VCC Undervoltage Lockout
Threshold VUVLO(VCC) Rising edge, IC disabled below this level
hysteresis = 200mV 3.8 4.1 4.4 V
CSL Discharge MOSFET OVP = VCC 16
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ELECTRICAL CHARACTERISTICS (continued)(VIN= 12V, VCC = VDD = VSHDN= VREFIN= 5V, VCSL= 1.8V, STDBY= SKIP= AGND, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CURRENT LIMITValley Current-Limit Threshold VLIMITVCSH - VCSL 17 20 25 mV
Current-Limit Threshold
(Negative) VNEG VCSH - VCSL,SKIP = VCC -23 mV
Current-Limit Threshold
(Zero Crossing) VZX VPGND1 - VLX 1 mV
SMPS GATE DRIVERSDH Gate Driver On-Resistance RDHBST - LX forced to 5V 1.5 5.0
DL high 1.5 5.0 DL Gate Driver On-Resistance RDL DL low 0.6 3.0
DH Gate Driver Source/
Sink Current IDH DH forced to 2.5V, BST - LX forced to 5V 1 A
IDL(SRC) DL forced to 2.5V 1 DL Gate Driver Source/
Sink Current IDL(SNK) DL forced to 2.5V 3 A
DL rising, TA = +25°C 10 25 Dead Time tDEAD DL falling, TA = +25°C 15 35 ns
Internal BST Switch
On-Resistance RBST IBST = 10mA,
VDD = 5V internal design target 4.5
LX, BST Leakage Current VBST = VLX = 26V, SHDN = AGND,
TA = +25°C 0.001 20 μA
INPUTS AND OUTPUTSLogic Input Threshold SHDN,STDBY,SKIP, OVP, rising edge
hysteresis = 300mV/600mV (min/max) 1.30 1.65 2.00 V
Logic Input Current SKIP = AGND or VCC, -1 +1 μA
Input Leakage Current VCSH = 0V or VCC, TA = +25°C -1 +1 μA
Input Bias Current VCSL = 0V or VCC 55 100 μA
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ELECTRICAL CHARACTERISTICS(VIN= 12V, VCC = VDD = VSHDN= VREFIN= 5V, VCSL= 1.8V, STDBY= SKIP= AGND, TA
= -40°C to +85°C, unless otherwise noted.)(Note 1)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
PWM CONTROLLERVIN3 26 Input Voltage Range VCC, VDD 4.5 5.5 V
FB = AGND 1.485 1.520
FB = VCC 1.782 1.820 Output Voltage Accuracy VCSL VIN = 4.5V to 26V,
SKIP = VCC
FB = Adj 0.990 1.020
RTON = 96.75k
(600kHz), 167ns
nominal
-15 +15
RTON = 200k
(300kHz), 333ns
nominal
-10 +10 On-Time Accuracy (Note 2) tONVIN= 12V,
VCSL= 1.2V
RTON = 303.25k
(200kHz), 500ns
nominal
-15 +15
Minimum Off-Time tOFF(MIN) (Note 2) 350 ns
FB forced above 1.0V (PWM, VTT, and
VTTR blocks); STDBY = VCC4 mA
Quiescent Supply Current (VCC) ICC
FB forced above 1.0V (ultra-skip and
VTTR blocks); STDBY = AGND 475 μA
LINEAR REGULATOR (VTT)VTTI Input Voltage Range VVTTI 1.0 2.8 V
VTTI Supply Current IVTTI VVTTI = 2.5V, VREFIN = 1.4V 50 μA
REFIN Range VREFIN 0.5 1.5 V
REFIN Disable Threshold VCC -
0.3 V
High-side on-resistance (source, IVTT = 0.1A) 0.25 VTT Internal MOSFET Low-side on-resistance (sink, IVTT = 0.1A) 0.36
VTT Load Regulation -50μA to -1A IVTT +50μA to +1A 17 mV/A
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ELECTRICAL CHARACTERISTICS (continued)(VIN= 12V, VCC = VDD = VSHDN= VREFIN= 5V, VCSL= 1.8V, STDBY= SKIP= AGND, TA
= -40°C to +85°C, unless otherwise noted.)(Note 1)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
REFERENCE BUFFER (VTTR)IVTT = ±1mA -10 +10 VTTR Output Accuracy (Adj) REFIN to VTTR
IVTT = ±3mA -20 +20
mV
IVTT = ±1mA -10 +10 VTTR Output Accuracy (Preset) VCSL/2 to VTTR IVTT = ±3mA -20 +20 mV
FAULT DETECTION (SMPS)PGOOD1 Output Low Voltage ISINK = 3mA 0.4 V
FAULT DETECTION (VTT)PGOOD2 Output Low Voltage ISINK = 3mA 0.4 V
FAULT DETECTIONVCC Undervoltage-Lockout
Threshold VUVLO(VCC) Rising edge, IC disabled below this level;
hysteresis = 200mV 4.0 4.4 V
CURRENT LIMITValley Current-Limit Threshold VLIMITVCSH - VCSL 15 25 mV
SMPS GATE DRIVERSDH Gate Driver On-Resistance RDHBST - LX forced to 5V 5
DL high 5 DL Gate Driver On-Resistance RDL DL low 3
DL rising 10 Dead Time tDEAD DL falling 15 ns
INPUTS AND OUTPUTSLogic Input Threshold SHDN,STDBY,SKIP, OVP, rising edge
hysteresis = 300mV/600mV (min/max) 1.3 2 V
Note 1:Limits are 100% production tested at TA= +25°C. Maximum and minimum limits over temperature are guaranteed by design
and characterization.
Note 2:On-time and off-time specifications are measured from 50% point at the DH pin with LX = GND, VBST= 5V, and a 250pF
capacitor connected from DH to LX. Actual in-circuit times might differ due to MOSFET switching speeds.
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Typical Operating Characteristics(MAX17000 Circuit of Figure 1, VIN = 12V, VDD= VCC= 5V, SKIP= GND, TA = +25°C, unless otherwise noted.)
SMPS 1.8V EFFICIENCY
vs. LOAD CURRENTMAX17000 toc01
LOAD CURRENT (A)
EFFICIENCY (%)0.1
STANDBY MODE
PWM MODE
VIN = 7V
SKIP MODE
SMPS 1.8V EFFICIENCY
vs. LOAD CURRENTMAX17000 toc02
LOAD CURRENT (A)
EFFICIENCY (%)0.1
STANDBY MODE
PWM MODE
VIN = 12V
SKIP MODE
SMPS 1.8V EFFICIENCY
vs. LOAD CURRENTMAX17000 toc03
LOAD CURRENT (A)
EFFICIENCY (%)0.1
STANDBY MODE
PWM MODE
VIN = 20V
SKIP MODE
SMPS 1.8V OUTPUT VOLTAGE
vs. LOAD CURRENTMAX17000 toc04
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
PWM MODE
VIN = 12V
SKIP MODE
SMPS SWITCHING FREQUENCY
vs. LOAD CURRENTMAX17000 toc05
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)82
VIN = 12V
VOUT = 1.8V
SMPS VALLEY-CURRENT LIMIT
vs. INPUT VOLTAGEMAX17000 toc06
INPUT VOLTAGE (V)
CURRENT LIMIT (A)1620248
RSENSE = 2mΩ
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGEMAX17000 toc07
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)1620248
PWM MODE, ICC + IDD
SKIP MODE, ICC + IDD
SKIP MODE, IIN
STANDBY MODE, ICC + IDD
STANDBY MODE, IIN
PWM MODE, IIN
NO LOAD
PRESET 1.5V OUTPUT
VOLTAGE DISTRIBUTIONMAX17000 toc08
OUTPUT VOLTAGE (V)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 150+85°C
+25°C
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
STARTUP WAVEFORM
(HEAVY LOAD)MAX17000 toc09
200μs/div
PGOOD1
SHDN : 5V/div
VDDQ : 500mV/div
VTT : 500mV/div
VTTR : 500mV/div
PGOOD1 : 2V/div
ILX : 5A/div
DL : 5V/div
RLOAD = 0.25Ω
SKIP = GND
VTTR
VTT
VDDQ
ILX
SHDN
SHUTDOWN WAVEFORM
(DISCHARGE MODE ENABLED)MAX17000 toc10
400μs/div
PGOOD2 : 5V/div
PGOOD1 : 5V/div
SHDN : 10V/div
ILX : 2A/div
DL : 5V/div
VDDQ : 2V/div
VTT : 1V/div
VTTR : 1V/div
VTTR
VTT
VDDQ
PGOOD1
PGOOD2
ILX
SHDN
STANDBY TRANSITION WAVEFORMMAX17000 toc11
2ms/div
TON
DL : 5V/div
LX : 10V/div
ILX : 2A/div
STBY : 5V/div
VDDQ : 1V/div
VTT : 1V/div
TON: 10V/div
VTTVDDQ
ILX
STBY
STANDBY TRANSITION WAVEFORMMAX17000 toc12
200μs/div
TON
LX : 10V/div
ILX : 10A/div
DL : 5V/div
STBY : 5V/div
VDDQ : 2V/div
VTT : 1V/div
TON: 10V/div
VTT
VDDQ
ILX
STBY
SMPS LOAD-TRANSIENT RESPONSE
(SKIP MODE)MAX17000 toc13
20μs/div
ILOAD : 5A/div
ILX : 5A/div
VDDQ : 50mV/div
LX : 10V/div
VDDQ
ILX
ILOAD
SMPS LOAD-TRANSIENT RESPONSE
(SKIP MODE)MAX17000 toc14
20μs/div
ILOAD : 5A/div
ILX : 5A/div
VDDQ : 50mV/div
LX : 10V/div
VDDQ
ILX
ILOAD
Typical Operating Characteristics (continued)(MAX17000 Circuit of Figure 1, VIN = 12V, VDD= VCC= 5V, SKIP= GND, TA = +25°C, unless otherwise noted.)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Typical Operating Characteristics (continued)(MAX17000 Circuit of Figure 1, VIN = 12V, VDD= VCC= 5V, SKIP= GND, TA = +25°C, unless otherwise noted.)
OUTPUT OVERLOAD WAVEFORMMAX17000 toc15
400μs/div
PGOOD2 : 2V/div
PGOOD1 : 2V/div
ILX : 10A/div
DL : 5V/div
VDDQ : 1V/div
VTT : 1V/div
VTTR : 1V/div
VDDQ
VTT
VTTR
ILX
PGOOD2
PGOOD1
VTT VOLTAGE
vs. SOURCE/SINK LOAD CURRENTMAX17000 toc16
LOAD CURRENT (A)
VTT VOLTAGE (V)
VTTI = 18V
VTT OFFSET VOLTAGE DISTRIBUTION
AT 300mA LOAD MAX17000 toc17
OFFSET VOLTAGE (mV)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 150+85°C
+25°C
VTT OVERLOAD FAULT WAVEFORMS
(5ms TIMER)MAX17000 toc20
1ms/div
VTTR : 1V/div
PGOOD1 : 2V/div
PGOOD2 : 2V/div
DL : 5V/div
ILX : 2A/div
VDDQ : 2V/div
VTT : 1V/div
VDDQ
VTT
VTTR
ILX
PGOOD1
PGOOD2
VTT SOURCE CURRENT LIMIT MAX17000 toc18
CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 150+85°C
+25°C
VTT SINK CURRENT LIMIT MAX17000 toc19
CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 150+85°C
+25°C
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
VTT LOAD-TRANSIENT RESPONSE (SOURCE)
IVTT BETWEEN 10mA AND 1.5AMAX17000 toc21
20μs/div
IVTT : 1A/div
VTT : 20mV/div
VTT_ac
IVTT
VDDQ = 1.8V
VTT LOAD-TRANSIENT RESPONSE
(SINK)MAX17000 toc22
20μs/div
IVTT : 1A/div
VTT : 20mV/div
VTT_ac
IVTT
VDDQ = 1.8V
VTT LOAD-TRANSIENT RESPONSE
(SOURCE/SINK)MAX17000 toc23
20μs/div
IVTT : 1A/div
VTT : 20mV/div
VTT_ac
IVTT
VDDQ = 1.8V
VTTR OUTPUT VOLTAGE
vs. LOAD CURRENTMAX17000 toc24
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)024-4
Typical Operating Characteristics (continued)
(MAX17000 Circuit of Figure 1, VIN = 12V, VDD= VCC= 5V, SKIP= GND, TA = +25°C, unless otherwise noted.)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Pin Description
PINNAMEFUNCTION1 OVP
OVP Mode Control. This input selectively enables/disables the SMPS OV protection feature and
output discharge mode. When enabled, the SMPS OV protection feature is enabled. Connect OVP to
the following voltage levels for the desired function:
High (> 2.4V) = Enable SMPS OV protection, and SMPS and VTT discharge FETs.
Low (AGND) = Disable SMPS OV protection, and SMPS and VTT discharge FETs.
2 PGOOD1
Open-Drain Power-Good Output. PGOOD1 is low when the SMPS output voltage is more than 15%
(typ) beyond the normal regulation point, during soft-start, and in shutdown.
After the soft-start circuit has terminated, PGOOD1 becomes high impedance if the SMPS output is
in regulation.
3 PGOOD2
Open-Drain Power-Good Output. PGOOD2 is low when the VTT output voltage is more than 10%
(typ) beyond the normal regulation point, in shutdown, in standby, and during soft-start.
After the SMPS soft-start circuit has terminated, PGOOD2 becomes high impedance if the VTT
output is in regulation. STDBY
Standby Control Input. When SHDN is high and STDBY is low, the MAX17000 enters a low-
quiescent current mode, putting the SMPS in ultra-skip operation and turning off the VTT output
(high-Z). This mode helps save converter power loss in computer standby operation.
When STDBY is high, normal SMPS operation resumes and the VTT output is enabled.
5 VTTS Sense Pin for Termination Supply Output. Normally connected to the VTT pin to allow accurate
regulation to VCSL/2 or the REFIN voltage.
6 VTTR
Termination Reference Buffer Output. VTTR tracks VCSL/2 when REFIN is connected to VCC. VTTR
tracks VREFIN when a voltage between 0.5V to 1.5V is set at REFIN. Decouple VTTR to AGND with a
0.33μF ceramic capacitor. PGND2 Power Ground for VTT. Connect PGND2 externally to the underside of the exposed pad.
8 VTT Termination Power-Supply Output. Connect VTT to VTTS to regulate the VTT voltage to the VTTS
regulation setting.
9 VTTI Termination Power-Supply Input. VTTI is the input power supply to the VTT linear regulator.
Normally connected to the output of the SMPS regulator for DDR applications.
10 REFIN
External Reference Input. REFIN sets the feedback regulation voltage (VTTR = VTTS = VREFIN) of
the MAX17000.
Connect REFIN to VCC to use the internal VCSL/2 divider.
Connect a 0.5V to 1.5V voltage input to set the adjustable output for VTT, VTTS, and VTTR.
11 FB
Feedback Input for SMPS Output. Connect to VCC for a fixed +1.8V output or to AGND for a fixed
+1.5V output. For an adjustable output (1.0V to 2.7V), connect FB to a resistive divider from the
output voltage. FB regulates to +1.0V.
12 CSL
Negative Input of the PWM Output Current-Sense and Supply Input for VTTR. Connect CSL to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
CSL is also the path for the internal 16 discharge MOSFET when VCC UVLO occurs with OVP
enabled.
13 CSH
Positive Input of the PWM Output Current Sense. Connect CSH to the positive side of the output
current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing.
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Pin Description (continued)
PINNAMEFUNCTION14 TON
Switching Frequency Setting Input. An external resistor between the input power source and this
pin sets the switching frequency per phase according to the following equation:
TSW = CTON x (RTON + 6.5k)
where CTON = 16.26pF.
TON is high impedance in shutdown.
15 DH High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.
16 LX Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure1.
17 BST Boost Flying Capacitor Connection. Connect to an external 0.1μF, 6V capacitor as shown in Figure
1. The MAX17000 contains an internal boost switch.
18 DL Synchronous-Rectifier Gate-Driver Output. DL swings from VDD to PGND1.
19 VDD
Supply Voltage Input for the DL Gate Driver and 3.3V Reference/Analog Supply. Connect to the
system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1μF or greater
ceramic capacitor.
20 PGND1 Power Ground. Ground connection for the low-side MOSFET gate driver.
21 AGND Analog Ground. Connect backside exposed pad to AGND.SKIP
Pulse-skipping Control Input. This input determines the mode of operation under normal steady-
state conditions and dynamic output voltage transitions:
High (> 2.4V) = Forced-PWM operation
Low (AGND) = Pulse-skipping mode
23 VCCController Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass VCC to AGND with a 1μF or
greater ceramic capacitor. SHDN
Shutdown Control Input. Connect to VCC for normal operation. When SHDN is pulled low, the
MAX17000 slowly ramps down the output voltage to ground. When the internal target voltage
reaches 25mV, the controller forces DL low, and enters the low current (1μA) shutdown state.
When discharge mode is enabled by OVP (OVP = high), the CSL and VTT internal 16 discharge
MOSFETs are enabled in shutdown. When discharge mode is disabled by OVP (OVP = low), LX,
VTT, and VTTR are high impedance in shutdown.
A rising edge on SHDN clears the fault OV protection latch.
— EP Exposed Pad. Connect backside exposed pad to AGND.
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Standard Application CircuitsThe MAX17000 standard application circuit (Figure 1)
generates the VDDQ, VTT, and VTTR rails for DDR,
DDR2, or DDR3 in a notebook computer. See Table 1 for
component selections. Table 2 lists the component man-
ufacturers. Table 3 is the operating mode truth table.
VOUT = 1.5V TO 1.8V AT 10AVOUT = 1.5V TO 1.8V AT 6ACOMPONENTVIN = 7V TO 20V (300kHz)VIN = 7V TO 16V (500kHz) Input Capacitor (2x) 10μF, 25V
Taiyo Yuden TMK432BJ106KM
10μF, 25V
Taiyo Yuden TMK432BJ106KM
Output Capacitor (2x) 330μF, 2.5V ,12m (C2 case)
SANYO 2R5TPE330MCC2
(2x) 220μF, 2.5V, 21m (B2 case)
SANYO 2R5TPE220MLB
Inductor 1.4μH, 12A, 3.4m (typ)
Sumida CDEP105(L)NP-1R4
1.4μH, 12A, 3.4m (typ)
Sumida CDEP105(L)NP-1R4
Current-Sensing Resistor 2m, 0.5W (2010)
Vishay WSL20102L000FEA
3m, 0.5W (2010)
Vishay WSL20103L000FEA
MOSFETs
30V, 20A n-channel MOSFET (high side)
Fairchild FDMS8690;
30V, 40A n-channel MOSFET (low side)
Fairchild FDMS8660S
30V 20A n-channel MOSFET (high side)
Fairchild FDMS8690;
30V 40A n-channel MOSFET (low side)
Fairchild FDMS8660S
Table 1. Component Selection for Standard Applications
SUPPLIERPHONEWEBSITE
INDUCTORSDale (Vishay) 402-563-6866 (USA) www.vishay.com
NEC/TOKIN America, Inc. 510-324-4110 (USA) www.nec-tokinamerica.com
Panasonic Corp. 65-231-3226 (Singapore), 408-749-9714 (USA) www.panasonic.com
Sumida Corp. 408-982-9660 (USA) www.sumida.com
TOKO America, Inc. 858-675-8013 (USA) www.tokoam.com
CAPACITORSAVX Corp. 843-448-9411 (USA) www.avxcorp.com
KEMET Corp. 408-986-0424 (USA) www.kemet.com
Panasonic Corp. 65-231-3226 (Singapore), 408-749-9714 (USA) www.panasonic.com
SANYO Electric Co., Ltd. 81-72-870-6310 (Japan), 619-661-6835 (USA) www.sanyodevice.com
Taiyo Yuden 03-3667-3408 (Japan), 408-573-4150 (USA) www.t-yuden.com
TDK Corp. 847-803-6100 (USA), 81-3-5201-7241 (Japan) www.component.tdk.com
SENSING RESISTORSVishay 402-563-6866 (USA) www.vishay.com
MOSFETFairchild Semiconductor 800-341-0392 (USA) www.fairchildsemi.com
DIODESCentral Semiconductor Corp. 631-435-1110 www.centralsemi.com
Nihon Inter Electronics Corp. 81-3-3343-84-3411 (Japan) www.niec.co.jp
Table 2. Component Suppliers
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management SolutionSHDNSTDBYSKIP
OPERATION 1 L H L H X
SMPS output ramps up in skip mode with a 1.4ms (typ) ramp time. PGOOD1 is held low until the
SMPS output is in regulation.
VTT and VTTR ramp up to the final voltage based on VCSL/2 or VREFIN. PGOOD2 is held low until
VTT is in regulation.
2 L H L X
SMPS output ramps up in skip mode with a 1.4ms ramp time. PGOOD1 is held low until the SMPS
output is in regulation.
Once CSL or FB is in regulation, the PWM block turns off and enters standby mode.
VTT remains off throughout sinceSTDBY is low. PGOOD2 stays low throughout. The VTT
discharge FET is enabled if OVP is high, but disabled if OVP is low.
VTTR ramps up to the final voltage based on VCSL/2 or VREFIN.
3 H L H X
Ultra-skip and standby modes are exited and the full current capability of the MAX17000 is
available.
VTT ramps up after the internal SMPS block is ready. VTT ramps to the final voltage based on
VCSL/2 or VREFIN.
PGOOD2 goes high when VTT is in regulation.
4 H H H
SMPS output is in forced-PWM mode.
VTT and VTTR are enabled.
PGOOD1 is high when the SMPS output is in regulation.
PGOOD2 is high when VTT is in regulation.
5 H H L
SMPS output is in normal skip mode.
VTT and VTTR are enabled.
PGOOD1 is high when the SMPS output is in regulation.
PGOOD2 is high when VTT is in regulation.
6 H L X
SMPS output is in ultra-skip mode.
VTT is off and is high impedance.
PGOOD2 is forced low.
VTTR is active and regulates to VCSL/2 or VREFIN.
7 H L H X Ultra-skip or skip mode is exited as the MAX17000 ramps the output down to zero.
VTTR tracks VCSL/2 or VREFIN during shutdown. After the SMPS output reaches 25mV, DL goes low.
8 H L L X
Ultra-skip or skip mode is exited as the MAX17000 ramps the output down to zero.
VTTR tracks VCSL/2 or VREFIN during shutdown. After the SMPS output reaches 25mV, DL goes
low. VTT is not enabled throughout soft-shutdown.
9 L X X DL low. Internal16 discharge MOSFETs on CSL and VTT enabled if OVP is high, but disabled if
OVP is low.
Table 3. Operating Mode Truth Table
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Detailed DescriptionThe MAX17000 complete DDR solution comprises a
step-down controller, a source/sink LDO regulator, and a
reference buffer. Maxim’s proprietary Quick-PWM pulse-
width modulator in the MAX17000 is specifically
designed for handling fast load steps while maintaining a
relatively constant operating frequency and inductor
operating point over a wide range of input voltages. The
Quick-PWM architecture circumvents the poor load-tran-
sient timing problems of fixed-frequency current-mode
PWMs, while also avoiding the problems caused by
widely varying switching frequencies in conventional con-
stant-on-time and constant-off-time PWM schemes.
Figure 1 is the MAX17000 standard application circuit
and Figure 2 is the MAX17000functional diagram.
The MAX17000 includes a ±2A source/sink LDO regu-
lator for the memory termination rail. The source/sink
regulator features a dead band that either sources or
sinks, ideal for the fast-changing short-period loads
presenting in memory termination applications. This
feature also reduces the VTT output capacitance
requirement down to 1μF, though load-transient
response can still require higher capacitance values
between 10μF and 20μF.
The reference buffer sources and sinks ±3mA, generating
a reference rail for use in the memory controller and
memory devices.
VDD
VCC
TON
ON/OFF
BST
VIN
7V TO 20V
VDDQ
+1.8V OR 1.5V
PGND1
CSL
CIN
RSENSE
RFBA
RFBB
CVTTI
CVTT
CVTTR
0.33µF
PGND2
VTTI
VTTR
VTTS
+5V
SLP_S3#
VTT
+1V TO + 2.5V
VTT = VDDQ/2
STDBY
SHDN
SKIP
REFIN
PGOOD2
+5V
PGOOD1
AGNDFB OPTIONS:
1. CONNECT FB TO 5V FOR FIXED +1.8V.
2. CONNECT FB TO GND FOR FIXED +1.5V.
3. USE FB RESISTOR-DIVIDER FOR ADJUSTABLE
OUTPUT VOLTAGES.
RTON
CSH
5V VCC
VCC
OVP1
AGNDPGND
CBST
0.1µF
100kΩ
100kΩ
10Ω
CVDD
1µF
CVCC
1µF
AGND
AGND
PGND
AGND
PGND
PGND
PGND
PGND
COUT
MAX17000
VTTR = VDDQ/2
Figure 1. MAX17000 Standard Application Circuit
