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MAX6874ETJ+
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
General DescriptionThe MAX6874/MAX6875 EEPROM-configurable, multi-
voltage supply sequencers/supervisors monitor several
voltage detector inputs and general-purpose logic
inputs, and provide programmable open-drain outputs
for highly configurable power-supply sequencing appli-
cations. The MAX6874 provides six voltage monitor
inputs, four general-purpose inputs, and eight program-
mable open-drain outputs. The MAX6875 provides four
voltage monitor inputs, three general-purpose inputs,
and five programmable open-drain outputs. Manual reset
and margin disable inputs provide additional flexibility.
All voltage detectors offer configurable thresholds for
undervoltage detection. One high-voltage input (IN1)
provides detector threshold voltages from +2.5V to
+13.2V in 50mV increments, or from +1.25V to +7.625V
in 25mV increments. A second positive input (IN2) pro-
vides detector threshold voltages from +2.5V to +5.5V
in 50mV increments, or from +1.25V to +3.05V in 25mV
increments. Positive inputs (IN3–IN6) provide detector
threshold voltages from +1V to +5.5V in 20mV incre-
ments, or from +0.5V to +3.05V in 10mV increments.
Programmable output stages control power-supply
sequencing or system resets/interrupts. Program the
open-drain outputs as active-high or active-low.
Programmable timing delay blocks configure each output
to wait between 25µs and 1600ms before deasserting.
An SMBus™/I2C-compatible serial data interface pro-
grams and communicates with the configuration EEP-
ROM, the configuration registers, and the internal 4kb
user EEPROM of the MAX6874/MAX6875.
The MAX6874/MAX6875 are available in a 7mm x 7mm
x 0.8mm 32-pin thin QFN package and operate over
the extended temperature range (-40°C to +85°C).
ApplicationsTelecommunications/Central Office Systems
Networking Systems
Servers/Workstations
Base Stations
Storage Equipment
Multimicroprocessor/Voltage Systems
FeaturesSix (MAX6874) or Four (MAX6875) Configurable
Input Voltage Detectors
One High Voltage Input (+1.25V to +7.625V or
+2.5V to +13.2V Thresholds)
One Voltage Input (+1.25V to +3.05V or
+2.5V to +5.5V)
Four (MAX6874) or Two (MAX6875) Positive
Voltage Inputs (+0.5V to +3.05V or +1V
to +5.5V)Four (MAX6874) or Three (MAX6875) General-
Purpose Logic InputsTwo Configurable Watchdog TimersEight (MAX6874) or Five (MAX6875) Programmable
Open-Drain Outputs
Active-High or Active-Low
Timing Delays from 25µs to 1600msMargining Disable and Manual Reset Controls4kb Internal User EEPROM
Endurance: 100,000 Erase/Write Cycles
Data Retention: 10 YearsI2C/SMBus-Compatible Serial Configuration/
Communication Interface±1% Threshold Accuracy
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Ordering Information19-3438; Rev 0; 10/04
EVALUATION KIT
AVAILABLE
Pin Configurations, TypicalOperating Circuit, and Selector
Guide appear at end of data sheet.
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODE
MAX6874ETJ-40°C to +85°C32 Thin QFNT3277-2
MAX6875ETJ-40°C to +85°C32 Thin QFNT3277-2
SMBus is a trademark of Intel Corp.
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VIN1= +6.5V to +13.2V, VIN2–VIN6= +2.7V to +5.5V, GPI_ = GND, MARGIN= MR= DBP, TA= -40°Cto +85°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND)
IN2–IN6, ABP, SDA, SCL, A0, A1,
GPI1–GPI4, MR, MARGIN, PO5–PO8
(MAX6874), PO3–PO5 (MAX6875)...................-0.3V to +6V
IN1, PO1–PO4 (MAX6874), PO1–PO2 (MAX6875)...-0.3V to +14V
DBP..........................................................................-0.3V to +3V
Input/Output Current (all pins)..........................................±20mA
Continuous Power Dissipation (TA= +70°C)
32-Pin 7mm x 7mm Thin QFN
(derate 33.3mW/°C above +70°C).............................2667mW
Operating Temperature Range...........................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYM BO LCONDITIONSMINTYPMAXUNITSVIN1Voltage on IN1 to ensure the device is fully
operational, IN3–IN6 = GND4.013.2
Operating Voltage Range
(Note 3)VIN3 to
VIN5
Voltage on any one of IN3–IN5 to ensure the
device is fully operational, IN1 = GND2.75.5
IN1 Supply Voltage
(Note 3)VIN1PMinimum voltage on IN1 to guarantee that the
device is powered through IN16.5V
Undervoltage LockoutVUVLOMinimum voltage on one of IN3–IN5 to
guarantee the device is EEPROM configured.2.5V
VIN1 = +13.2V, IN2–IN6 = GND, no load1.21.5mA
Supply CurrentICCWriting to configuration registers or EEPROM,
no load1.32mA
VIN1 (50mV increments)2.513.2
VIN1 (25mV increments)1.2507.625
VIN2 (50mV increments)2.505.5
VIN2 (25mV increments)1.2503.05
VIN3–VIN6 (20mV increments)1.05.5
Threshold RangeVTH
VIN3–VIN6 (10mV increments)0.503.05
TA = +25°C-1.0+1.0
Threshold AccuracyIN1–IN6, VIN_ fallingTA = -40°C to +85°C-1.5+1.5%
Threshold HysteresisVTH-HYST0.3% VTH
Reset Threshold Temperature
CoefficientΔVTH/°C10ppm/
Threshold-Voltage Differential
NonlinearityVTH DNL-1+1LSB
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSIN1 Input Leakage CurrentILIN1For VIN1 < the highest of VIN3–VIN5100140µA
IN2 Input ImpedanceRIN2160230320kΩ
IN3–IN6 Input ImpedanceRIN3 to
RIN6VIN1 > 6.5V70100145kΩ
Power-Up DelaytPUVABP ≥ VUVLO3.5ms
IN_ to PO_ DelaytDPOVIN_ falling or rising, 100mV overdrive25µs
00025µs
PO_ Timeout PeriodtRPRegister contents
(Table 16)
VABP ≥ +2.5V, ISINK = 500µA0.3PO1–PO4 (MAX6874), PO1–PO2
(MAX6875) Output Low (Note 3)VOLVABP ≥ +4.0V, ISINK = 2mA0.4V
VABP ≥ +2.5V, ISINK = 1mA0.3PO5–PO8 (MAX6874), PO3–PO5
(MAX6875) Output Low (Note 3)VOLVABP ≥ +4.0V, ISINK = 4mA0.4V
PO1–PO8 Output Initial Pulldown
CurrentIPDVABP ≤ VUVLO, VPO_ = 0.8V1040µA
PO1–PO8 Output Open-Drain
Leakage CurrentILKGOutput high impedance-1+1µA
ELECTRICAL CHARACTERISTICS (continued)(VIN1= +6.5V to +13.2V, VIN2–VIN6= +2.7V to +5.5V, GPI_ = GND, MARGIN= MR= DBP, TA= -40°Cto +85°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Notes 1, 2)
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITSVIL0.8MR, MARGIN, GPI_ Input VoltageVIH1.4V
MR Input Pulse WidthtMR1µs
MR Glitch Rejection100ns
MR to PO_ DelaytDMR2µs
MR to VDBP Pullup CurrentIMRV MR = +1.4V51015µA
MARGIN to VDBP Pullup CurrentIMARGINV MARGIN = +1.4V51015µA
GPI_ to PO_ DelaytDGPI_200ns
GPI_ Pulldown CurrentIGPI_VGPI_ = +0.8V51015µA
Watchdog Input Pulse WidthtWDIGPI_ configured as a watchdog input50ns
Watchdog Timeout PeriodtWDRegister Contents
(Table 19)
SERIAL INTERFACE LOGIC (SDA, SCL, A0, A1)
Logic-Input Low VoltageVIL0.8V
Logic-Input High VoltageVIH2.0V
Input Leakage CurrentILKG-1+1µA
Output Voltage LowVOLISINK = 3mA0.4V
Input/Output CapacitanceCI/O10pF
ELECTRICAL CHARACTERISTICS (continued)(VIN1= +6.5V to +13.2V, VIN2–VIN6= +2.7V to +5.5V, GPI_ = GND, MARGIN= MR= DBP, TA= -40°Cto +85°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Notes 1, 2)
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Note 1:Specifications guaranteed for the stated global conditions. The device also meets the parameters specified when 0 < VIN1
< +6.5V, and at least one of VIN3–VIN6is between +2.7V and +5.5V, while the remaining VIN3–VIN6are between 0 and
+5.5V.
Note 2:Device may be supplied from any one of IN_, except IN2 and IN6.
Note 3:The internal supply voltage, measured at ABP, equals the maximum of IN3–IN5 if VIN1= 0, or equals +5.4V if VIN1> +6.5V.
For +4V < VIN1< +6.5V and VIN3–VIN5> +2.7V, the input that powers the device cannot be determined.
Note 4:CBUS= total capacitance of one bus line in pF. Rise and fall times are measured between 0.1 x VBUSand 0.9 x VBUS.
Note 5:Input filters on SDA, SCL, A0, and A1 suppress noise spikes < 50ns.
Note 6:An additional cycle is required when writing to configuration memory for the first time.
TIMING CHARACTERISTICS(IN1 = GND, VIN2–VIN6= +2.7V to +5.5V, GPI_ = GND, MARGIN= MR= DBP, TA= -40°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.) (Notes 1, 2)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICS (Figure 2)Serial Clock FrequencyfSCL400kHz
Clock Low PeriodtLOW1.3µs
Clock High PeriodtHIGH0.6µs
Bus-Free TimetBUF1.3µs
START Setup TimetSU:STA0.6µs
START Hold TimetHD:STA0.6µs
STOP Setup TimetSU:STO0.6µs
Data-In Setup TimetSU:DAT100ns
Data-In Hold TimetHD:DAT0900ns
Receive SCL/SDA Minimum Rise TimetR(Note 4)
20 +
0.1 x
CBUS
Receive SCL/SDA Maximum Rise TimetR(Note 4)300ns
Receive SCL/SDA Minimum Fall TimetF(Note 4)
20 +
0.1 x
CBUS
Receive SCL/SDA Maximum Fall TimetF(Note 4)300ns
Transmit SDA Fall TimetFCBUS = 400pF
20 +
0.1 x
CBUS
300ns
Pulse Width of Spike SuppressedtSP(Note 5)50ns
EEPROM Byte Write Cycle TimetWR(Note 6)11ms
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Typical Operating Characteristics(VIN1= +6.5V to +13.2V, VIN2–VIN6= +2.7V to +5.5V, GPI_ = GND, MARGIN= MR= DBP, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (IN1)MAX6874/75 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TA = +85°C
TA = +25°C
TA = -40°C
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (IN3 TO IN5)MAX6874/75 toc02
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TA = +25°C
TA = +85°C
TA = -40°C
NORMALIZED PO_ TIMEOUT PERIOD
vs. TEMPERATUREMAX6874/753 toc03
TEMPERATURE (°C)
NORMALIZED PO_ TIMEOUT PERIOD35-1510
IN_ TO PO_
PROPAGATION DELAY vs. TEMPERATURE
MAX6874/75 toc04
TEMPERATURE (°C)
IN_ TO PO_ OUTPUT PROPAGATION DELAY (3510-15
100mV OVERDRIVE
NORMALIZED WATCHDOG TIMEOUT PERIOD
vs. TEMPERATUREMAX6874/75 toc05
TEMPERATURE (°C)
NORMALIZED WATCHDOG TIMEOUT PERIOD35-1510
NORMALIZED IN_ THRESHOLD
vs. TEMPERATURE
MAX6874/75 toc06
TEMPERATURE (°C)
NORMALIZED IN_ THRESHOLD3510-15
IN3 THRESHOLD = 1V,
20mV/STEP RANGE
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
MAXIMUM IN_ TRANSIENT DURATION
vs. IN_ THRESHOLD OVERDRIVEMAX6874/75 toc07
IN_ THRESHOLD OVERDRIVE (mV)
MAXIMUM IN_ TRANSIENT DURATION (
PO_ ASSERTION
OCCURS ABOVE THIS LINE
OUTPUT VOLTAGE LOW
vs. SINK CURRENTMAX6874/75 toc08
ISINK (mA)
(mV)121011345678912
PO1–PO4 (MAX6874)
PO1–PO2 (MAX6875)
PO5–PO8 (MAX6874)
PO3–PO5 (MAX6875)
Typical Operating Characteristics (continued)(VIN1= +6.5V to +13.2V, VIN2–VIN6= +2.7V to +5.5V, GPI_ = GND, MARGIN= MR= DBP, TA= +25°C, unless otherwise noted.)
MR TO PO_ PROPAGATION DELAY
vs. TEMPERATUREMAX6874/75 toc09
TEMPERATURE (°C)
MR TO PO_ PROPAGATION DELAY (35-1510
MAXIMUM MR TRANSIENT DURATION
vs. MR THRESHOLD OVERDRIVE
MAX6874/75 toc10
MR THRESHOLD OVERDRIVE (mV)
MAXIMUM MR TRANSIENT DURATION (
PO_ ASSERTION OCCURS
ABOVE THIS LINE
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Pin Description
PIN
MAX6874MAX6875NAMEFUNCTIONPO2
Programmable Output 2. Configurable active-high or active-low open-drain output. PO2 pulls
low with a 10µA internal current sink for +1V < VABP < VUVLO. PO2 assumes its programmed
conditional output state when ABP exceeds UVLO.PO3
Programmable Output 3. Configurable active-high or active-low open-drain output. PO3 pulls
low with a 10µA internal current sink for +1V < VABP < VUVLO. PO3 assumes its programmed
conditional output state when ABP exceeds UVLO.PO4
Programmable Output 4. Configurable active-high or active-low open-drain output. PO4 pulls
low with a 10µA internal current sink for +1V < VABP < VUVLO. PO4 assumes its programmed
conditional output state when ABP exceeds UVLO.GNDGroundPO5
Programmable Output 5. Configurable active-high or active-low open-drain output. PO5 pulls
low with a 10µA internal current sink for +1V < VABP < VUVLO. PO5 assumes its programmed
conditional output state when ABP exceeds UVLO.PO6
Programmable Output 6. Configurable active-high or active-low open-drain output. PO6 pulls
low with a 10µA internal current sink for +1V < VABP < VUVLO. PO6 assumes its programmed
conditional output state when ABP exceeds UVLO.PO7
Programmable Output 7. Configurable active-high or active-low open-drain output. PO7 pulls
low with a 10µA internal current sink for +1V < VABP < VUVLO. PO7 assumes its programmed
conditional output state when ABP exceeds UVLO.PO8
Programmable Output 8. Configurable active-high or active-low open-drain output. PO8 pulls
low with a 10µA internal current sink for +1V < VABP < VUVLO. PO8 assumes its programmed
conditional output state when ABP exceeds UVLO.
9, 10, 23,
1, 8, 9,10,
16, 17,
23–26, 32
N.C.No Connection. Not internally connected.11MARGIN
Margin Input. Drive MARGIN low to hold PO_ in their existing states. Leave MARGIN
unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the same
time. MARGIN is internally pulled up to DBP through a 10µA current source.12MR
Manual Reset Input. MR to either assert PO_ into a programmed state or to have no effect on
PO_ when driving MR low (see Table 6). Leave MR unconnected or connect to DBP if unused.
MR is internally pulled up to DBP through a 10µA current source.13SDASerial Data Input/Output (Open-Drain). SDA requires an external pullup resistor.14SCLSerial Clock Input. SCL requires an external pullup resistor.15A0Address Input 0. Address inputs allow up to four MAX6874 or two MAX6875 connections on
one common bus. Connect A0 to GND or to the serial interface power supply.—A1Address Input 1 (MAX6874 only). Address inputs allow up to four MAX6874 connections on
one common bus. Connect A1 to GND or to the serial interface power supply.
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Pin Description (continued)
PIN
MAX6874MAX6875NAMEFUNCTION—GPI4General-Purpose Logic Input 4 (MAX6874 Only). An internal 10µA current source pulls GPI4 to
GND. Configure GPI4 to control watchdog timer functions or the programmable outputs.18GPI3General-Purpose Logic Input 3. An internal 10µA current source pulls GPI3 to GND. Configure
GPI3 to control watchdog timer functions or the programmable outputs.19GPI2General-Purpose Logic Input 2. An internal 10µA current source pulls GPI2 to GND. Configure
GPI2 to control watchdog timer functions or the programmable outputs.20GPI1General-Purpose Logic Input 1. An internal 10µA current source pulls GPI1 to GND. Configure
GPI1 to control watchdog timer functions or the programmable outputs.21ABP
Internal Power-Supply Output. Bypass ABP to GND with a 1µF ceramic capacitor. ABP powers
the internal circuitry of the MAX6874/MAX6875. Do not use ABP to supply power to external
circuitry.22DBP
Internal Digital Power-Supply Output. Bypass DBP to GND with a 1µF ceramic capacitor. DBP
supplies power to the EEPROM memory and the internal logic circuitry. Do not use DBP to
supply power to external circuitry.—IN6
Voltage Input 6. Configure IN6 to detect voltage thresholds between +1V and +5.5V in 20mV
increments, or +0.5V to +3.05V in 10mV increments. For improved noise immunity, bypass IN6
to GND with a 0.1µF capacitor installed as close to the device as possible.—IN5
Voltage Input 5. Configure IN5 to detect voltage thresholds between +1V and +5.5V in 20mV
increments, or +0.5V to +3.05V in 10mV increments. For improved noise immunity, bypass IN5
to GND with a 0.1µF capacitor installed as close to the device as possible.27IN4
Voltage Input 4. Configure IN4 to detect voltage thresholds between +1V and +5.5V in 20mV
increments, or +0.5V to +3.05V in 10mV increments. For improved noise immunity, bypass IN4
to GND with a 0.1µF capacitor installed as close to the device as possible.28IN3
Voltage Input 3. Configure IN3 to detect voltage thresholds between +1V and +5.5V in 20mV
increments, or +0.5V to +3.05V in 10mV increments. For improved noise immunity, bypass IN3
to GND with a 0.1µF capacitor installed as close to the device as possible.29IN2
Voltage Input 2. Configure IN2 to detect voltage thresholds from +2.5V to +5.5V in 50mV
increments or +1.25V to +3.05V in 25mV increments. For improved noise immunity, bypass IN2
to GND with a 0.1µF capacitor installed as close to the device as possible.30IN1
High-Voltage Input 1. Configure IN1 to detect voltage thresholds from +2.5V to +13.2V in 50mV
increments or +1.25V to +7.6V in 25mV increments. For improved noise immunity, bypass IN1
to GND with a 0.1µF capacitor installed as close to the device as possible.31I.C.Internal Connection. Leave unconnected.2PO1
Programmable Output 1. Configurable active-high or active-low open-drain output. PO1 pulls
low with a 10µA internal current sink for +1V < VABP < VUVLO. PO1 assumes its programmed
conditional output state when ABP exceeds UVLO.EPExposed Paddle. Exposed paddle is internally connected to GND.
MAX6874/MAX6875
Detailed DescriptionThe MAX6874/MAX6875 EEPROM-configurable, multi-
voltage supply sequencers/supervisors monitor several
voltage detector inputs and general-purpose logic
inputs, and feature programmable outputs for highly
configurable power-supply sequencing applications.
The MAX6874 features six voltage detector inputs, four
general-purpose logic inputs, and eight programmable
outputs, while the MAX6875 features four voltage
detector inputs, three general-purpose logic inputs,
and five programmable outputs. Manual reset and mar-
gin disable inputs simplify board-level testing during
the manufacturing process. The MAX6874/MAX6875
feature an accurate internal 1.25V reference.
All voltage detectors provide configurable thresholds for
undervoltage detection. One high-voltage input (IN1)
provides detector threshold voltages from +1.25V to
+7.625V in 25mV increments or +2.5V to +13.2V in 50mV
increments. A positive input (IN2) provides detector
threshold voltages from +1.25V to +3.05V in 25mV incre-
ments or +2.5V to +5.5V in 50mV increments. Positive
inputs (IN3–IN6) provide detector threshold voltages
from +0.5V to +3.05V in 10mV increments or +1.0V to
+5.5V in 20mV increments.
The host controller communicates with the MAX6874/
MAX6875’s internal 4kb user EEPROM, configuration
EEPROM, and configuration registers through an
SMBus/I2C-compatible serial interface (see Figure1).
Program the open-drain outputs as active-high or active-
low. Program each output to assert on any voltage detec-
tor input, general-purpose logic input, watchdog timer,
manual reset, or other output stages. Programmable tim-
ing delay blocks configure each output to wait between
25µs and 1600ms before de-asserting.
The MAX6874/MAX6875 feature a watchdog timer,
adding flexibility. Program the watchdog timer to assert
one or more programmable outputs. Program the watch-
dog timer to clear on a combination of one GPI_ input
and one programmable output, one of the GPI_ inputs
only, or one of the programmable outputs only. The initial
and normal watchdog timeout periods are independently
programmable from 6.25ms to 102.4s.
A virtual diode-ORing scheme selects the input that pow-
ers the MAX6874/MAX6875. The MAX6874/MAX6875
derive power from IN1 if VIN1> +6.5V or from the highest
voltage on IN3–IN5 if VIN1< +2.7V. The power source
cannot be determined if +4V < VIN1< +6.5V and one
of VIN3through VIN5> +2.7V. The programmable out-
puts maintain the correct programmed logic state for
VABP> VUVLO. One of IN3 through IN5 must be
greater than +2.7V or IN1 must be greater than +4V for
device operation.
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors COMPARATORS
REGISTER BANK
CONTROLLER
EEPROM
(USER AND
CONFIG)
OUTPUT
STAGESLOGIC NETWORK
FOR PO_
WATCHDOG
TIMERGPI_
GPI_, MR,
MARGIN
PO_IN_
SDA,
SCL
ANALOG
BLOCK
DIGITAL
BLOCK
SERIAL
INTERFACE
Figure1. Top-Level Block Diagram
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors MAX6874
MAX6875
1.25V
VREF
IN2 DETECTOR
IN_ DETECTORIN1
IN2
IN3
IN4
IN5
(N.C.)
IN6
(N.C.)
IN3 DETECTOR
IN4 DETECTOR
IN5 DETECTOR
IN6 DETECTOR
PROGRAMMABLE
ARRAYTIMING BLOCK 2
TIMING BLOCK 3
TIMING BLOCK 4
TIMING BLOCK 5
TIMING BLOCK 6
TIMING BLOCK 7
TIMING BLOCK 8
PO2 OUTPUT
PO3 OUTPUT
PO4 OUTPUT
PO5 OUTPUT
PO6 OUTPUT
PO7 OUTPUT
PO8 OUTPUT
TIMING BLOCK 1
GPI1GPI2GPI3GPI4 (N.C.)MARGINMR
PO1
PO2
PO3
PO4
PO5
PO6
(N.C.)
PO7
(N.C.)
PO8
(N.C.)
MAIN
OSCILLATOR
SERIAL
INTERFACE
SDA
SCL
(N.C.)
EEPROM
CHARGE PUMP
CONFIG
REGISTERS
CONFIG
EEPROM
USER
EEPROM
1µF
ABP
DBP
1µF
2.55V
LDO
5.4V
LDO
(VIRTUAL
DIODES)
GND( ) ARE FOR MAX6875 ONLY.
PO_ OUTPUT
Functional Diagram
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Powering the MAX6874/MAX6875The MAX6874/MAX6875 derive power from the positive
voltage-detector inputs: IN1 or IN3–IN5. A virtual diode-
ORing scheme selects the positive input that supplies
power to the device (see the Functional Diagram). IN1
must be at least +4V or one of IN3–IN5 (MAX6874)/
IN3–IN4 (MAX6875) must be at least +2.7V to ensure
device operation. An internal LDO regulates IN1 down
to +5.4V.
The highest input voltage on IN3–IN5 (MAX6874)/
IN3–IN4 (MAX6875) supplies power to the device, unless
VIN1≥+6.5V, in which case IN1 supplies power to the
device. For +4V < VIN1< +6.5V and one of VIN3through
VIN5> +2.7V, the input power source cannot be deter-
mined due to the dropout voltage of the LDO. Internal
hysteresis ensures that the supply input that initially pow-
ered the device continues to power the device when
multiple input voltages are within 50mV of each other.
ABP powers the analog circuitry; bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. The internal supply voltage, mea-
sured at ABP, equals the maximum of IN3–IN5
(MAX6874)/IN3–IN4 (MAX6875) if VIN1= 0, or equals
+5.4V when VIN1> +6.5V. Do not use ABP to provide
power to external circuitry.
The MAX6874/MAX6875 also generate a digital supply
voltage (DBP) for the internal logic circuitry and the
EEPROM; bypass DBP to GND with a 1µF ceramic
capacitor installed as close to the device as possible.
The nominal DBP output voltage is +2.55V. Do not use
DBP to provide power to external circuitry.
InputsThe MAX6874/MAX6875 contain multiple logic and volt-
age-detector inputs. Table1 summarizes these various
inputs.
Set the threshold voltages for each voltage-detector
input with registers 00h–05h. Each threshold voltage is
an undervoltage threshold. Set the threshold range for
each voltage detector with register 0Dh.
Table1. Programmable Features
FEATUREDESCRIPTIONHigh-Voltage Input
(IN1)Undervoltage threshold+2.5V to +13.2V threshold in 50mV increments+1.25V to +7.625V threshold in 25mV increments
Voltage Input (IN2)Undervoltage threshold+2.5V to +5.5V threshold in 50mV increments+1.25V to +3.05V threshold in 25mV increments
Voltage Input
IN3–IN6 (MAX6874),
IN3–IN4 (MAX6875)Undervoltage threshold+1V to +5.5V threshold in 20mV increments+0.5V to +3.05V threshold in 10mV increments
Programmable Outputs
PO1–PO8 (MAX6874),
PO1–PO5 (MAX6875)Active high or active lowOpen-drain outputDependent on MR, MARGIN, IN_, GPI1–GPI4 , WD, and/or PO_Programmable timeout periods of 25µs, 1.5625ms, 6.25ms, 25ms, 50ms, 200ms, 400ms, or 1.6s
General-Purpose
Logic Inputs,
GPI1–GPI4 (MAX6874),
GPI1–GPI3 (MAX6875)Active-high or active-low logic levelsConfigure GPI_ as inputs to watchdog timers or programmable output stages
Watchdog TimerClear dependent on any combination of one GPI_ input and one programmable output, a GPI_ input
only, or a programmable output onlyInitial watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4sNormal watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4sWatchdog enable/disable
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
High-Voltage Input (IN1)IN1 offers threshold voltages of +2.5V to +13.2V in
50mV increments, or +1.25V to +7.625V in 25mV incre-
ments. Use the following equations to set the threshold
voltages for IN1:
where VTHis the desired threshold voltage and x is the
decimal code for the desired threshold (Table2). For
the +2.5V to +13.2V range, x must equal 214 or less,
otherwise the threshold exceeds the maximum operat-
ing voltage of IN1.
IN2IN2 offers thresholds from +2.5V to +5.5V in 50mV
increments, or +1.25V to +3.05V in 25mV increments.
Use the following equations to set the threshold volt-
ages for IN2:
where VTHis the desired threshold voltage and x is the
decimal code for the desired threshold (Table3).
For the +2.5V to +5.5V range, x must equal 60 or less,
otherwise the threshold exceeds the maximum operat-
ing voltage of IN2. For the +1V to +3.05V range, x must
equal 72 or less.
IN3–IN6IN3–IN6 offer positive voltage detectors monitor volt-
ages from +1V to +5.5V in 20mV increments, or +0.5V
to +3.05V in 10mV increments. Use the following equa-
tions to set the threshold voltages for IN_:
where VTHis the desired threshold voltage and x is the
decimal code for the desired threshold (Table4). For
the +1V to +5.5V range, x must equal 225 or less, oth-
erwise the threshold exceeds the maximum operating
voltage of IN3–IN6.VVforVtoVrangeTH=++− . . . 05
00105305VVforVtoVrangeTH=++− . 1
002155VVforVtoVrangeTH=++− . . . 125025125305VVforVtoVrangeTH=++− . . . 25
0052555VVforVtoVrangeTH=++− . . . 1250251257625VVforVtoVrangeTH=++− . . . 25
FEATUREDESCRIPTION
Manual Reset Input
(MR)Forces PO_ into the active output state when MR = GNDPO_ deassert after MR releases high and the PO_ timeout period expiresPO_ cannot be a function of MR only
Write Disable• Locks user EEPROM based on PO_
Configuration Lock• Locks configuration EEPROM
Table1. Programmable Features (continued)
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Table2. IN1 Threshold Settings
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGEDESCRIPTION00h8000h[7:0]IN1 detector threshold (V1) (see equations in the High-Voltage Input (IN1) section).
0Dh800Dh[0]IN 1 r ang e sel ecti on:
0 = 2.5V to 13.2V r ang e i n 50m V i ncr em ents. 1 = 1.25V to 7.625V r ang e i n 25m V i ncr em ents.
Table3. IN2 Threshold Settings
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGEDESCRIPTION01h8001h[7:0]IN2 detector threshold (V2) (see equations in the IN2 section).
0Dh800Dh[7:6]
IN2 range selection:
00 = Not used.
01 = Not used.
10 = +2.5V to +5.5V range in 50mV increments.
11 = +1.25V to +3.05V range in 25mV increments.
Table4. IN3–IN6 Threshold Settings
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGEDESCRIPTION02h8002h[7:0]IN3 detector threshold (V3) (see equations in the IN3–IN6 section).
03h8003h[7:0]IN4 detector threshold (V4) (see equations in the IN3–IN6 section).
04h8004h[7:0]IN5 (MAX6874 only) detector threshold (V5)
(see equations in the IN3–IN6 section).
05h8005h[7:0]IN6 (MAX6874 only) detector threshold (V6)
(see equations in the IN3–IN6 section).
[1]IN 3 r ang e sel ecti on:
0 = + 1V to + 5.5V r ang e i n 20m V i ncr em ents. 1 = + 0.5V to + 3.05V r ang e i n 10m V i ncr em ents.
[2]IN 4 r ang e sel ecti on:
0 = + 1V to + 5.5V r ang e i n 20m V i ncr em ents. 1 = + 0.5V to + 3.05V r ang e i n 10m V i ncr em ents.
[3]IN 5 ( M AX 6874 onl y) r ang e sel ecti on:
0 = + 1V to + 5.5V r ang e i n 20m V i ncr em ents. 1 = + 0.5V to + 3.05V r ang e i n 10m V i ncr em ents.
[4]IN 6 ( M AX 6874 onl y) r ang e sel ecti on:
0 = + 1V to + 5.5V r ang e i n 20m V i ncr em ents. 1 = + 0.5V to + 3.05V r ang e i n 10m V i ncr em ents.
0Dh800Dh
[5]Not used.
GPI1–GPI4 (MAX6874)/GPI1–GPI3 (MAX6875)The GPI1–GPI4 programmable logic inputs control
power-supply sequencing (programmable outputs),
reset/interrupt signaling, and watchdog functions (see
the Configuring the Watchdog Timer (Registers
3Ch–3Dh) section). Configure GPI1–GPI4 for active-low
or active-high logic (Table5). GPI1–GPI4 internally pull
down to GND through a 10µA current sink.
The manual reset (MR) input initiates a reset condition.
Register 40h determines the programmable outputs that
assert while MRis low (Table 6). All affected program-
mable outputs remain asserted (see the Programmable
Outputs section) for their PO_ timeout periods after MR
releases high. An internal 10µA current source pulls MR
to DBP. Leave MRunconnected or connect to DBP if
unused. A programmable output cannot depend solely
on MR.
MARGIN
MARGINallows system-level testing while power supplies
exceed the normal ranges. Drive MARGINlow to hold the
programmable outputs in their state while system-level
testing occurs. Leave MARGINunconnected or connect
to DBP if unused. An internal 10µA current source pulls
MARGINto DBP. The state of each programmable output
does not change while MARGIN= GND. MARGINover-
rides MRif both assert at the same time.
Programmable OutputsThe MAX6874 features eight programmable outputs
while the MAX6875 features five programmable outputs.
Program the open-drain outputs as active-high or
active-low. During power-up, the programmable outputs
pull to GND with an internal 10µA current sink for 1V <
VABP< VUVLO. The programmable outputs remain in
their active states until their respective timeout periods
(PO_) expire and all of the programmed conditions are
met for each output. Any output programmed to depend
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Table5. GPI1–GPI4 Active Logic States
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGEDESCRIPTION[0]GPI1. 0 = active low. 1 = active high.
[1]GPI2. 0 = active low. 1 = active high.
[2]GPI3. 0 = active low. 1 = active high.3Bh803Bh
[3]GPI4 (MAX6874 only). 0 = active low. 1 = active high.
Table6. Programmable Output Behavior and MR
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGEDESCRIPTION[0]PO1 (MAX6874 only). 0 = PO1 independent of MR. 1 = PO1 asserts when MR = low.
[1]PO2 (MAX6874 only). 0 = PO2 independent of MR. 1 = PO2 asserts when MR = low.
[2]PO3 (MAX6874)/PO1 (MAX6875). 0 = PO3/PO1 independent of MR.
1 = PO3/PO1 asserts when MR = low.
[3]PO4 (MAX6874)/PO2 (MAX6875). 0 = PO4/PO2 independent of MR.
1 = PO4/PO2 asserts when MR = low.
[4]PO5 (MAX6874)/PO3 (MAX6875). 0 = PO5/PO3 independent of MR.
1 = PO5/PO3 asserts when MR = low.
[5]PO6 (MAX6874)/PO4 (MAX6875). 0 = PO6/PO4 independent of MR.
1 = PO6/PO4 asserts when MR = low.
[6]PO7 (MAX6874)/PO5 (MAX6875). 0 = PO7/PO5 independent of MR.
1 = PO7/PO5 asserts when MR = low.
40h8040h
[7]PO8 (MAX6874 only). 0 = PO8 independent of MR. 1 = PO8 asserts when MR = low.
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors on no condition always remains in its active state (Table
19). An output configured as active-high is considered
asserted when that output is logic high. No output can
depend solely on MR.
The voltage monitors generate fault signals (logical 0) to
the MAX6874/MAX6875s’ logic array when an input volt-
age is below the programmed undervoltage threshold.
Registers 0Eh through 3Ah and 40h configure each of the
programmable outputs. Programmable timing blocks set
the PO_ timeout period from 25µs to 1600ms for each
programmable output. See register 3Ah (Table15) to set
the active state (active-high or active-low) for each pro-
grammable output and Table 16 for timeout periods for
each output.
For example, PO3 (MAX6874—Table9) may depend on
the IN1 undervoltage threshold, and the states of GPI1,
PO1, and PO2. Write a one to R16h[0], R17h[6], and
R18h[3:2] to configure the output as indicated. IN1 must
be above the undervoltage threshold (Table2), GPI1
must be inactive (Table5), and PO1 (Tables 7 and 15)
and PO2 (Table 9) must be in their deasserted states for
the output to deassert.
Table7 only applies to PO1 of the MAX6874. Write a 0
to a bit to make the PO1 output independent of the
respective signal (IN1–IN6 thresholds, WD, GPI1–GPI4,
MR, or other programmable outputs).
Table7. PO1 (MAX6874 Only) Output Dependency
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BITOUTPUT ASSERTION CONDITIONS[0]1 = PO1 assertion depends on IN1 undervoltage threshold (Table 2).
[1]1 = PO1 assertion depends on IN2 undervoltage threshold (Table 3).
[2]1 = PO1 assertion depends on IN3 undervoltage threshold (Table 4).
[3]1 = PO1 assertion depends on IN4 undervoltage threshold (Table 4).
[4]1 = PO1 assertion depends on IN5 undervoltage threshold (Table 4).
[5]1 = PO1 assertion depends on IN6 undervoltage threshold (Table 4).
[6]1 = PO1 assertion depends on watchdog (Tables 19 and 20).
0Eh800Eh
[7]M ust b e set to 0.
[5:0]M ust b e set to 0.
[6]1 = PO1 assertion depends on GPI1 (Table 5).0Fh800Fh
[7]1 = PO1 assertion depends on GPI2 (Table 5).
[0]1 = PO1 assertion depends on GPI3 (Table 5).
[1]1 = PO1 assertion depends on GPI4 (Table 5).
[2]1 = PO1 assertion depends on PO2 (Table 8).
[3]1 = PO1 assertion depends on PO3 (Table 9).
[4]1 = PO1 assertion depends on PO4 (Table 10).
[5]1 = PO1 assertion depends on PO5 (Table 11).
[6]1 = PO1 assertion depends on PO6 (Table 12).
10h8010h
[7]1 = PO1 assertion depends on PO7 (Table 13).
11h8011h[0]1 = PO1 assertion depends on PO8 (Table 14).
40h8040h[0]1 = PO1 asserts when MR = low (Table 6).
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors Table8 only applies to PO2 of the MAX6874. Write a 0
to a bit to make the PO2 output independent of the
respective signal (IN1–IN6 thresholds, WD, GPI1–GPI4,
MR, or other programmable outputs).
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BITOUTPUT ASSERTION CONDITIONS[0]1 = PO2 assertion depends on IN1 undervoltage threshold (Table 2).
[1]1 = PO2 assertion depends on IN2 undervoltage threshold (Table 3).
[2]1 = PO2 assertion depends on IN3 undervoltage threshold (Table 4).
[3]1 = PO2 assertion depends on IN4 undervoltage threshold (Table 4).
[4]1 = PO2 assertion depends on IN5 undervoltage threshold (Table 4).
[5]1 = PO2 assertion depends on IN6 undervoltage threshold (Table 4).
[6]1 = PO2 assertion depends on watchdog (Tables 18 and 19).
12h8012h
[7]M ust b e set to 0.
[5:0]M ust b e set to 0.
[6]1 = PO2 assertion depends on GPI1 (Table 5).13h8013h
[7]1 = PO2 assertion depends on GPI2 (Table 5).
[0]1 = PO2 assertion depends on GPI3 (Table 5).
[1]1 = PO2 assertion depends on GPI4 (Table 5).
[2]1 = PO2 assertion depends on PO1 (Table 7).
[3]1 = PO2 assertion depends on PO3 (Table 9).
[4]1 = PO2 assertion depends on PO4 (Table 10).
[5]1 = PO2 assertion depends on PO5 (Table 11).
[6]1 = PO2 assertion depends on PO6 (Table 12).
14h8014h
[7]1 = PO2 assertion depends on PO7 (Table 13).
15h8015h[0]1 = PO2 assertion depends on PO8 (Table 14).
40h8040h[1]1 = PO2 asserts when MR = low (Table 6).
Table8. PO2 (MAX6874 Only) Output Dependency
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors Table9 only applies to PO3 of the MAX6874 and PO1
of the MAX6875. Write a 0 to a bit to make the PO3/PO1
output independent of the respective signal (IN_
thresholds, WD, GPI1–GPI4, MR, or other programma-
ble outputs).
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BITOUTPUT ASSERTION CONDITIONS[0]1 = PO3/PO1 assertion depends on IN1 undervoltage threshold (Table 2).
[1]1 = PO3/PO1 assertion depends on IN2 undervoltage threshold (Table 3).
[2]1 = PO3/PO1 assertion depends on IN3 undervoltage threshold (Table 4).
[3]1 = PO3/PO1 assertion depends on IN4 undervoltage threshold (Table 4).
[4]1 = PO3 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be
set to 0 for the MAX6875.
[5]1 = PO3 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be
set to 0 for the MAX6875.
[6]1 = PO3/PO1 assertion depends on watchdog (Tables 18 and 19).
16h8016h
[7]M ust b e set to 0.
[5:0]M ust b e set to 0.
[6]1 = PO3/PO1 assertion depends on GPI1 (Table 5).17h8017h
[7]1 = PO3/PO1 assertion depends on GPI2 (Table 5).
[0]1 = PO3/PO1 assertion depends on GPI3 (Table 5).
[1]1 = PO3/PO1 assertion depends on GPI4 (Table 5).
[2]1 = P O3 ( M AX 6874 onl y) asser ti on d ep end s on P O1 ( Tab l e 7) . M ust b e set to 0 for the M AX 6875.
[3]1 = P O3 ( M AX 6874 onl y) asser ti on d ep end s on P O2 ( Tab l e 8) . M ust b e set to 0 for the M AX 6875.
[4]1 = PO3/PO1 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10).
[5]1 = P O3/P O 1 asser ti on d ep end s on P O5 ( M AX 6874) /P O 3 ( M AX 6875) ( Tab l e 11) .
[6]1 = PO3/PO1 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12).
18h8018h
[7]1 = PO3/PO1 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13).
1Ch801Ch[1:0]1 = P O3 ( M AX 6874 onl y) asser ti on d ep end s on P O8 ( Tab l e 14) . M ust b e set to 0 for the M AX 6875.
40h8040h[2]1 = PO3/PO1 asserts when MR = low (Table 6).
Table9. PO3 (MAX6874)/PO1 (MAX6875) Output Dependency
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors Table10 only applies to PO4 of the MAX6874 and PO2
of the MAX6875. Write a 0 to a bit to make the PO4/PO2
output independent of the respective signal (IN_
thresholds, WD, GPI1–GPI4, MR, or other programma-
ble outputs).
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BITOUTPUT ASSERTION CONDITIONS[0]1 = PO4/PO2 assertion depends on IN1 undervoltage threshold (Table 2).
[1]1 = PO4/PO2 assertion depends on IN2 undervoltage threshold (Table 3).
[2]1 = PO4/PO2 assertion depends on IN3 undervoltage threshold (Table 4).
[3]1 = PO4/PO2 assertion depends on IN4 undervoltage threshold (Table 4).
[4]1 = P O4 ( M AX 6874 onl y) asser ti on d ep end s on IN 5 und er vol tag e thr eshol d ( Tab l e 4) . M ust b e set
to 0 for the M AX 6875.
[5]1 = P O4 ( M AX 6874 onl y) asser ti on d ep end s on IN 6 und er vol tag e thr eshol d ( Tab l e 4) . M ust b e set
to 0 for the M AX 6875.
[6]1 = PO4/PO2 assertion depends on watchdog (Tables 18 and 19).
1Dh801Dh
[7]M ust b e set to 0.
[5:0]M ust b e set to 0.
[6]1 = PO4/PO2 assertion depends on GPI1 (Table 5).1Eh801Eh
[7]1 = PO4/PO2 assertion depends on GPI2 (Table 5).
[0]1 = PO4/PO2 assertion depends on GPI3 (Table 5).
[1]1 = PO4/PO2 assertion depends on GPI4 (Table 5).
[2]1 = P O4 ( M AX 6874 onl y) asser ti on d ep end s on P O1 ( Tab l e 7) . M ust b e set to 0 for the M AX 6875.
[3]1 = P O4 ( M AX 6874 onl y) asser ti on d ep end s on P O2 ( Tab l e 8) . M ust b e set to 0 for the M AX 6875.
[4]1 = P O4/P O 2 asser ti on d ep end s on P O3 ( M AX 6874) /P O 1 ( M AX 6875) ( Tab l e 9) .
[5]1 = P O4/P O 2 asser ti on d ep end s on P O5 ( M AX 6874) /P O 3 ( M AX 6875) ( Tab l e 11) .
[6]1 = P O4/P O 2 asser ti on d ep end s on P O6 ( M AX 6874) /P O 4 ( M AX 6875) ( Tab l e 12) .
1Fh801Fh
[7]1 = PO4/PO2 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13).
23h8023h[0]1 = P O4 ( M AX 6874 onl y) asser ti on d ep end s on P O8 ( Tab l e 14) . M ust b e set to 0 for the M AX 6875.
40h8040h[3]1 = PO4/PO2 asserts when MR = low (Table 6).
Table10. PO4 (MAX6874)/PO2 (MAX6875) Output Dependency
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors Table11 only applies to PO5 of the MAX6874 and PO3
of the MAX6875. Write a 0 to a bit to make the PO5/PO3
output independent of the respective signal (IN_
thresholds, WD, GPI1–GPI4, MR, or other programma-
ble outputs).
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BITOUTPUT ASSERTION CONDITIONS[0]1 = PO5/PO3 assertion depends on IN1 undervoltage threshold (Table 2).
[1]1 = PO5/PO3 assertion depends on IN2 undervoltage threshold (Table 3).
[2]1 = PO5/PO3 assertion depends on IN3 undervoltage threshold (Table 4).
[3]1 = PO5/PO3 assertion depends on IN4 undervoltage threshold (Table 4).
[4]1 = PO5 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be
set to 0 for the MAX6875.
[5]1 = PO5 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be
set to 0 for the MAX6875.
[6]1 = PO5/PO3 assertion depends on watchdog (Tables 18 and 19).
24h8024h
[7]M ust b e set to 0.
[5:0]M ust b e set to 0.
[6]1 = PO5/PO3 assertion depends on GPI1 (Table 5).25h8025h
[7]1 = PO5/PO3 assertion depends on GPI2 (Table 5).
[0]1 = PO5/PO3 assertion depends on GPI3 (Table 5).
[1]1 = PO5/PO3 assertion depends on GPI4 (Table 5).
[2]1 = P O5 ( M AX 6874 onl y) asser ti on d ep end s on P O1 ( Tab l e 7) . M ust b e set to 0 for the M AX 6875.
[3]1 = P O5 ( M AX 6874 onl y) asser ti on d ep end s on P O2 ( Tab l e 8) . M ust b e set to 0 for the M AX 6875.
[4]1 = PO5/PO3 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9).
[5]1 = PO5/PO3 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10).
[6]1 = PO5/PO3 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12).
26h8026h
[7]1 = PO5/PO3 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13).
2Ah802Ah[0]1 = P O5 ( M AX 6874 onl y) asser ti on d ep end s on P O8 ( Tab l e 14) . M ust b e set to 0 for the M AX 6875.
40h8040h[4]1 = PO5/PO3 asserts when MR = low (Table 6).
Table11. PO5 (MAX6874)/PO3 (MAX6875) Output Dependency
