MAX9388EUP+ ,Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffersapplications, and feature♦ 0.3ps(RMS) Random Jitterextremely low propagation delays (318ps, typ) an ..
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MAX9388EUP+
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
General DescriptionThe MAX9386/MAX9387/MAX9388 are fully differential,
high-speed, low-jitter ECL/PECL multiplexers (muxes)
with output buffer(s). The devices are designed for
clock-and-data distribution applications, and feature
extremely low propagation delays (318ps, typ) and out-
put-to-output skews (3.9ps, typ). The MAX9386 is a 5:1
mux with a single output buffer. The MAX9387 is a 5:1
mux with dual output buffers, and is intended for use in
redundant systems. The MAX9388 is a 4:1 mux with a
single output buffer, and is pin compatible with the
MC100EP57.
Three single-ended select inputs, SEL0, SEL1, and
SEL2, control the mux function on the MAX9386/
MAX9387. The MAX9388 has two select inputs, SEL0
and SEL1. The mux select inputs are compatible with
ECL/PECL logic, and are internally referenced to the
on-chip output VBB, nominally VCC- 1.425V. The select
inputs accept signals between VCCand VEE. Internal
pulldowns to VEEensure a low-default condition if the
select inputs are left open.
The differential inputs D_, D_can be configured to
accept a single-ended signal when the unused comple-
mentary input is connected to the on-chip reference
output VBB. All the differential inputs have internal bias
and clamping circuits that ensure low-default output
states when the inputs are left open.
The MAX9386/MAX9387/MAX9388 operate with a wide
supply range |VCC- VEE|of 2.375V to 5.5V. The
MAX9386/MAX9388 are offered in 20-pin TSSOP and
QSOP packages. The MAX9387 is offered in 24-pin
TSSOP and QSOP packages.
ApplicationsHigh-Speed Telecom and Datacom Applications
Central Office Backplane Clock Distribution
DSLAM/DLC
Features318ps (typ) Propagation Delay>2.7GHz Toggle Frequency0.3ps(RMS) Random Jitter<14ps (max) at +25°C Output-to-Output Skew
(MAX9387)-2.375V to -5.5V Supplies for Differential
LVECL/ECL+2.375V to +5.5V Supplies for Differential
LVPECL/PECLOutputs Low for Open InputsDual Output Buffers (MAX9387)Pin Compatible with MC100EP57 (MAX9388EUP)>2kV ESD Protection (Human Body Model)
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers19-2617; Rev 1; 12/02
Ordering Information
PART
TEMP
RANGE
PIN-
PACKAGESELECTION
MAX9386EUP-40°C to +85°C20 TSSOP5:1 mux with 1
output buffer
MAX9386EEP*-40°C to +85°C20 QSOP5:1 mux with 1
output buffer
VCC
SEL2
SEL1
SEL0D1
TOP VIEW
VCC
VBB1D3
VBB2
VEED4
MAX9386
TSSOP/QSOP
Pin ConfigurationsPin Configurations continued at end of data sheet.
Ordering Information continued at end of data sheet.*Future product—contact factory for availability.
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC- VEE...............................................................-0.3V to +6.0V
Inputs (D_, D_, SEL_) to VEE......................-0.3V to (VCC+ 0.3V)
D_ to D_..............................................................................±3.0V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
VBB_Sink/Source Current ...............................................±600µA
Continuous Power Dissipation (TA= +70°C)
20-Lead TSSOP (derate 11.0mW/°C above +70°C)....880mW
θJAin Still Air...........................................................+91°C/W
θJC...........................................................................+20°C/W
24-Lead TSSOP (derate 12.2mW/°C above +70°C)....976mW
θJAin Still Air...........................................................+82°C/WJC...........................................................................+15°C/W
20-Lead QSOP (derate 9.1mW/°C above +70°C).......727mW
θJAin Still Air.........................................................+110°C/W
θJC...........................................................................+34°C/W
24-Lead QSOP (derate 9.5mW/°C above +70°C).......762mW
θJAin Still Air.........................................................+105°C/W
θJC...........................................................................+34°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (D_, D_, Q_, Q_, SEL_, VBB_) .............≥2kV
Lead Temperature (soldering, 10s).................................+300°C
DC ELECTRICAL CHARACTERISTICS(VCC- VEE= 2.375V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V. Typical values are at VCC- VEE= 3.3V, VIHD= VCC- 1V,
VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1–4)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS
INPUT (D_, D_, SEL_)Single-Ended
Input High
Voltage
VIH
VBB connected to
the unused input
(Figure 1)
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
0.880V
Single-Ended
Input Low
Voltage
VIL
VBB connected to
the unused input
(Figure 1)
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
1.625V
Differential Input
High VoltageVIHDFigure 1VEE +
1.2VCCVEE +
1.2VCCVEE +
1.2VCCV
Differential Input
Low VoltageVILDFigure 1VEEVCC -
0.095VEEVCC -
0.095VEEVCC -
0.095V
VCC - VEE
< 3.0V0.095VCC -
VEE0.095VCC -
VEE0.095VCC -
VEEDifferential Input
VoltageV I H D - V I LD Figure 1
VCC - VEE
≥ 3.0V0.0953.0000.0953.0000.0953.000
Input CurrentIINVIH, VIL, VIHD, VILD-100+100-100+100-100+100µA
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
AC ELECTRICAL CHARACTERISTICS(VCC- VEE= 2.375V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V, VIHD- VILD= 0.15V to 1V, fIN≤2.5GHz input duty cycle
= 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC- VEE= 3.3V, VIHD= VCC- 1V, VILD= VCC- 1.5V, fIN=
622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITSDifferential
Input-to-Output
Delay
tPLHD,
tPHLDFigure 2222309377238318395254333431ps
SEL_-to-Output
Delay
tPLH2,
tPHL2
Figure 4, input
transition time = 500ps
(20% to 80%) (Note 8)
1.641.41.6ns
Output-to-
Output SkewtSKOOMAX9387 only, Figure 5
(Note 9)3.9263.9148.026ps
Input-to-Output
SkewtSKIOFigure 6 (Note 10)7.3537.7508.350psar t- to- P ar t S kew tSKPP(Note 11)111130133ps
DC ELECTRICAL CHARACTERISTICS (continued)(VCC- VEE= 2.375V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V. Typical values are at VCC- VEE= 3.3V, VIHD= VCC- 1V,
VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1–4)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS
OUTPUT (Q_, Q_)Single-Ended
Output High
Voltage
VOHFigure 2VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
0.895V
Single-Ended
Output Low
Voltage
VOLFigure 2VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
1.695V
Differential
Output VoltageV OH - V OLFigure 2650830650840650840mV
REFERENCE OUTPUT (VBB_ )Reference
Voltage Output
VBB1,
VBB2
IBB1 + IBB2 = ±0.5mA
(Note 5)
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
1.325V
POWER SUPPLYMAX9386345036503850
MAX9387406042604560Supply Current
(Note 6)IEE
MAX9388314733473547
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:Current into an I/O pin is defined as positive. Current out of an I/O pin is defined as negative.
Note 3:DC parameters production tested at TA= +25°C and guaranteed by design over the full operating temperature range.
Note 4:Single-ended data input operation using VBB_is limited to (VCC- VEE) ≥3.0V.
Note 5:Use VBB_only for inputs that are on the same device as the VBB_reference.
Note 6:All pins open except VCCand VEE.
Note 7:Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8:Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal.
Note 9:Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 10:Measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of the
differential input signal.
Note 11:Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge
transition.
Note 12:Device jitter added to the differential input signal.
AC ELECTRICAL CHARACTERISTICS (continued)VCC- VEE= 2.375V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V, VIHD- VILD= 0.15V to 1V, fIN≤2.5GHz input duty cycle
= 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC- VEE= 3.3V, VIHD= VCC- 1V, VILD= VCC- 1.5V, fIN=
622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITSfIN = 156M H z0.31.150.31.150.31.15
fIN = 622M H z0.31.150.31.150.31.15Added Random
Jitter (Note 12)tRJClock
pattern
fIN = 2.5GH z0.31.150.31.150.31.15
ps(RMS)
fIN = 156M b p s339533953395Added
Deterministic
Jitter (Note 12)
TDJPRBS23 - 1fIN = 622M b p s216121612161
psP-P
Switching
FrequencyfMAXVOH - VOL ≥ 300mV,
Figure 22.72.72.7GHz
Select Toggle
FrequencyfSEL100100100MHz
Output Rise and
Fall Time (20%
to 80%)
tR, tFFigure 2671051387411715581128165ps
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
Typical Operating Characteristics(VCC- VEE= 3.3V, VIHD= VCC- 1V, VILD= VCC- 1.5V, outputs loaded with 50Ω±1% to VCC - 2V, fIN = 1.5GHz, input duty cycle =
50%, input transition time = 125ps (20% to 80%), unless otherwise noted.)
SUPPLY CURRENT (IEE)
vs. TEMPERATUREMAX9386 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)35-1510
OUTPUT AMPLITUDE (VOH - VOL)
vs. FREQUENCY
MAX9386 toc02
FREQUENCY (MHz)
OUTPUT VOLTAGE (mV)
OUTPUT RISE/FALL
vs. TEMPERATURE
MAX9386 toc03
TEMPERATURE (°C)
RISE/FALL TIME (ps)3510-15
FALL
RISE
DIFFERENTIAL PROPAGATION DELAY
vs. INPUT HIGH VOLTAGEMAX9386 toc04
INPUT HIGH VOLTAGE (V)
PROPAGATION DELAY (ps)
tPLHD
tPHLD
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATUREMAX9386 toc05
TEMPERATURE (°C)
TRANSITION TIME (ps)3510-15
tPLHD
tPHLD
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
PIN
MAX9386MAX9388
NAMEFUNCTION2D0Noninverting Differential Input 0. Internal 250kΩ to VCC and 150kΩ to VEE.D0Inverting Differential Input 0. Internal 150kΩ to VCC and 150kΩ to VEE.4D1Noninverting Differential Input 1. Internal 250kΩ to VCC and 150kΩ to VEE.D1Inverting Differential Input 1. Internal 150kΩ to VCC and 150kΩ to VEE.6D2Noninverting Differential Input 2. Internal 250kΩ to VCC and 150kΩ to VEE.D2Inverting Differential Input 2. Internal 150kΩ to VCC and 150kΩ to VEE.8D3Noninverting Differential Input 3. Internal 250kΩ to VCC and 150kΩ to VEE.D3Inverting Differential Input 3. Internal 150kΩ to VCC and 150kΩ to VEE.—D4Noninverting Differential Input 4. Internal 250kΩ to VCC and 150kΩ to VEE.—D4Inverting Differential Input 4. Internal 150kΩ to VCC and 150kΩ to VEE.10, 11VEENegative Supply12VBB2
Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a
reference for single-ended operation. When used, bypass VBB2 to VCC with a 0.01µF ceramic
capacitor. Otherwise leave open.13VBB1
Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a
reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01µF ceramic
capacitor. Otherwise leave open.
14, 201, 14
17, 20VCC
Positive Supply. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the
device.15QInverting Output. Typically terminate with 50Ω resistor to VCC - 2V.16QNoninverting Output. Typically terminate with 50Ω resistor to VCC - 2V.18SEL0Select Logic Input 0. Internal 120kΩ pulldown to VEE.19SEL1Select Logic Input 1. Internal 120kΩ pulldown to VEE.—SEL2Select Logic Input 2. Internal 120kΩ pulldown to VEE.
MAX9386/MAX9388 Pin Description
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
PIN
MAX9387
NAMEFUNCTION1, 18, 24VCCPositive Supply. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors
as close to the device as possible with the smaller value capacitor closest to the device.D0Noninverting Differential Input 0. Internal 250kΩ to VCC and 150kΩ to VEE.D0Inverting Differential Input 0. Internal 150kΩ to VCC and 150kΩ to VEE.D1Noninverting Differential Input 1. Internal 250kΩ to VCC and 150kΩ to VEE.D1Inverting Differential Input 1. Internal 150kΩ to VCC and 150kΩ to VEE.D2Noninverting Differential Input 2. Internal 250kΩ to VCC and 150kΩ to VEE.D2Inverting Differential Input 2. Internal 150kΩ to VCC and 150kΩ to VEE.D3Noninverting Differential Input 3. Internal 250kΩ to VCC and 150kΩ to VEE.D3Inverting Differential Input 3. Internal 150kΩ to VCC and 150kΩ to VEE.D4Noninverting Differential Input 4. Internal 250kΩ to VCC and 150kΩ to VEE.D4Inverting Differential Input 4. Internal 150kΩ to VCC and 150kΩ to VEE.
12, 13VEENegative SupplyVBB2
Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a reference for
single-ended operation. When used, bypass VBB2 to VCC with a 0.01µF ceramic capacitor. Otherwise
leave open.VBB1
Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a reference for
single-ended operation. When used, bypass VBB1 to VCC with a 0.01µF ceramic capacitor. Otherwise
leave open.Q1Inverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.Q1Noninverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.Q0Inverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.Q0Noninverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.SEL0Select Logic Input 0. Internal 120kΩ pulldown to VEE.SEL1Select Logic Input 1. Internal 120kΩ pulldown to VEE.SEL2Select Logic Input 2. Internal 120kΩ pulldown to VEE.
MAX9387 Pin Description
