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MAXQ7665BATM+
16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems
General DescriptionThe MAXQ7665A–MAXQ7665D smart systems-on-a-chip
(SoC) are data-acquisition systems based on a micro-controller (μC). As members of the MAXQ® family of 16-bit, reduced instruction set computing (RISC) μCs, the MAXQ7665A–MAXQ7665D are ideal for low-cost, low-power, embedded applications such as industrial controls and building automation. The flexible, modular architecture design used in these μCs allows development of targeted products for specific applications with minimal effort.
The MAXQ7665A–MAXQ7665D incorporate a high-perfor-mance 16-bit RISC core, a 12-bit 500ksps SAR ADC with a programmable gain amplifier (PGA), and a full CAN 2.0B controller supporting transfer rates up to 1Mbps. These devices include a 12-bit DAC with a buffered voltage output and on-chip oscillator circuitry to operate from an external high-frequency (8MHz) crystal. There is also a built-in internal RC oscillator as an alternative to using an external crystal. The MAXQ7665A–MAXQ7665D contain an inter-
nal temperature sensor to measure die temperature and a remote temperature-sensor driver. The analog functions and digital I/O are powered from a +5V supply, while the internal digital core is powered from +3.3V, which can be supplied by an on-chip linear regulator. These devices also include a dual power-supply supervisor with reset and a JTAG interface for in-system programming and debugging. The 16-bit RISC μC includes up to 128KB (64K x 16) of flash memory and 512 bytes (256 x 16) of RAM.
The MAXQ7665A–MAXQ7665D are available in a 7mm x 7mm 48-pin TQFN package and are specified to operate from -40°C to +125°C.
Applications●Industrial Control
Features●
High-Performance, Low-Power, 16-Bit RISC Core 8MHz Operation, Approaching 1MIPS per MHz Low Power (< 3mA/MIPS, DVDD = +3.3V) 16-Bit Instruction Word, 16-Bit Data Bus 33 Instructions (Most Require Only One Clock Cycle) 16-Level Hardware Stack Three Independent Data Pointers with Automatic
Increment/Decrement
●
Program and Data Memory Up to 128KB (64K x 16) Internal Flash 512 Bytes (256 x 16) Internal RAM
●
Smart Analog Peripherals Low-Power, Eight Differential-Channel, 12-Bit, 500ksps ADC Programmable-Gain Amplifier, Software-Selectable Gain: 1V/V, 2V/V, 4V/V, 8V/V, 16V/V, 32V/V 12-Bit DAC with Buffered Voltage Output External References for ADC and DAC Internal (Die) and External Diode Temperature Sensing
●
Timer/Digital I/O Peripherals Full CAN 2.0B Controller 15 Message Centers (256-Byte Dual Port Memory) Programmable Bit Rates from 10kbps to 1Mbps Standard 11-Bit or Extended 29-Bit Identification
Modes Two Data Masks and Associated IDs for DeviceNET™, SDS and Other Higher Layer CAN Protocols External Transmit Disable for Autobaud SIESTA Low-Power Mode Wake-Up on CANRXD Edge Transition UART (LIN) with User-Programmable Baud Rate 16 x 16 Hardware Multiplier with 48-Bit Accumulator, Single Clock Cycle Operation Three 16-Bit (or Six 8-Bit) Programmable Timer/Counter/PWM Eight General-Purpose, Digital I/O Pins, with External Interrupt Capability All Interrupts Can Be Used as a Wake-Up
●
Crystal/Clock Module Internal Oscillator for Use with External Crystal On-Chip RC Oscillator Eliminates External Crystal External Clock-Source Operation Programmable Watchdog Timer
●
Power-Management Module Power-On Reset (POR) Power-Supply Supervisor/Brownout Detection for Digital I/O and Digital Core Supplies On-Chip +3.3V, 50mA Linear Regulator
●
JTAG Interface Extensive Debug and Emulation Support
In-System Test Capability Flash-Memory-Program Download Software Bootstrap Loader for Flash Programming
●
Ultra-Low-Power Consumption Low-Power, Stop Mode (CPU Shutdown)
Ordering Information and Pin Configuration appear at end
of data sheet.MAXQ is a registered trademark of Maxim Integrated Products, Inc.
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition SystemsNote: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maximintegrated.com/errata.
EVALUATION KIT AVAILABLE
DVDD to DGND, AGND, or GNDIO .........................-0.3V to +4VDGND to GNDIO or AGND ..................................-0.3V to +0.3VDVDDIO to DGND, AGND, or GNDIO .....................-0.3V to +6VAVDD to DGND, AGND, or GNDIO .........................-0.3V to +6VDigital Inputs/Outputs to DGND, AGND, or GNDIO ............................................................-0.3V to (DVDDIO + 0.3V)Analog Inputs/Outputs to DGND, AGND, or GNDIO ................................................................-0.3V to (AVDD + 0.3V)
RESET, XIN, XOUT to DGND, AGND, or GNDIO ................................................................-0.3V to (DVDD + 0.3V)
Continuous Current into Any Pin ......................................±50mAContinuous Power Dissipation (TA = +70°C) 48-Pin TQFN (derate 40mW/°C above +70°C) .........3200mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIRMENTSSupply Voltage Range
DVDDSafe mode (RC/2 = 3.8MHz)2.73.33.6Normal mode3.03.33.6
AVDD4.755.05.25
DVDDIO4.755.05.25
AVDD Supply CurrentIAVDDShutdown (Note 2)0.110µA
All analog functions enabled6.78mA
Analog Module Subfunction
Incremental Supply Current
ADC enabled, fADC = 1ksps, fSYSCLK = 8MHz4.2
ADC enabled, fADC = 500ksps, fSYSCLK = 8MHz1890
DAC enabled (zero scale)305
Internal temperature sensor enabled502
Additional current when one or more of the
ADC, DAC, and/or temperature sensor is
enabled (only counted once) 128
PGA enabled4.5mA
DVDD Supply CurrentIDVDD
CPU in stop mode, all peripherals disabled320µA
High-speed mode (Note 3)28Flash erase or write mode3550
DVDD Module Subfunction
Incremental Supply Current
DVDD supervisor and brownout monitor 2HF crystal oscillator150
Internal RC oscillator200
DVDDIO Supply CurrentIDVDDIOAll digital I/Os static at GND or DVDDIO 10(Note 4)1000
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
MEMORY SECTIONFlash Memory Size
MAXQ7665A128MAXQ7665B64
MAXQ7665C48
MAXQ7665D32
Flash Erase/Write Endurance
DVDD = +3V, at +25°C1MCycles
DVDD = +3V, at +85°C100kCycles
DVDD = +3V, at +125°C100kCycles
Flash Erase TimingOne sector0.715s
Flash Program TimingSingle word11360µs
Entire lash1.54.5s
Flash Data Retention Time
TA = +125°C, single write20
YearsFirst 100,000 cycles at +25°C, then retention
tested at TA = +125°C10
RAM Memory Size512Bytes
Utility ROM Size4096Words
ANALOG SENSE PATHResolutionNADCNo missing codes12Bits
Integral NonlinearityINLADC
Gain = 1, bipolar mode, VIN = ±2500mV,
500ksps±0.5±4.0
LSB
Gain = 8, unipolar mode, VIN = +400mV, 142ksps±2.0
Gain = 16, bipolar mode, VIN = ±156mV, 142ksps±2.0±4.0
Gain = 32, bipolar mode, VIN = ±50mV, 142ksps±2.0
Differential NonlinearityDNLADC
Gain = 1, bipolar, VIN = ±2500mV, 500ksps±1.0
LSBGain = 16, bipolar, VIN = ±156mV, 142ksps±1.0
All other gain settings±0.6
Offset ErrorInput referred±2.5±5mV
Offset-Error Temperature Coeficient±8µV/°C
Zero-Code ErrorBipolar, differential measurement of error for ideal ADC output of 0x000±2.5mV
Gain ErrorExclude offset and reference error-1.0+1.0%
Gain-Error Temperature Coeficient±8.5ppm/°C
Signal-to-Noise Plus DistortionSINADPGA gain = 1V/V-71dB
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Electrical Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSpurious-Free Dynamic RangeSFDRPGA gain = 1V/V-91dB
Conversion Clock FrequencyfADCCLKfSYSCLK = 8MHz0.58.0MHz
Sample RatefSAMPLE
PGA gain = 1V/V, RSOURCE ≤ 1kΩ500
kspsAny PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ142
Conversion TimetCONVtACQ plus 13 ADCCLK cycles at 8MHztACQ + 1.625µs
Channel/Gain Select Plus Conversion Time
PGA gain = 1V/V, RSOURCE ≤ 1kΩ2µsAny PGA gain setting, RSOURCE ≤ 5kΩ7
Track-and-Hold Acquisition TimetACQ
PGA gain = 1V/V, RSOURCE ≤ 1kΩ375ns
Any PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ5µs
Turn-On TimetRECOV5µs
Aperture Delay30ns
Aperture Jitter50psP-P
Input-Voltage Range
Unipolar mode
PGA gain = 10AVDD
PGA gain = 201.6
PGA gain = 400.8
PGA gain = 800.4
PGA gain = 1600.2
PGA gain = 3200.1
Bipolar mode, AIN+ to AIN-
PGA gain = 1-VREFADC +VREFADC
PGA gain = 2-VREFADC /4+VREFADC /4
PGA gain = 4-VREFADC /8+VREFADC /8
PGA gain = 8-VREFADC
/16+VREFADC
/16
PGA gain = 16-VREFADC /32+VREFADC /32
PGA gain = 32-VREFADC /64+VREFADC /64
Absolute Input-Voltage RangeAGNDAVDDV
Input Leakage CurrentAIN15–AIN0±20nA
Small-Signal Bandwidth (-3dB)VIN x gain = 100mVP-P
PGA gain = 1180
MHz
PGA gain = 2140
PGA gain = 4120
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Electrical Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSLarge-Signal Bandwidth (-3dB)VIN x gain = 3.2VP-P
PGA gain = 1180
kHz
PGA gain = 2140
PGA gain = 4120
PGA gain = 8100
PGA gain = 1682
PGA gain = 3280
Input CapacitanceSingle-ended, any input of AIN0 to AIN15
PGA gain = 113.6
PGA gain = 22
PGA gain = 44
PGA gain = 88
PGA gain = 1616
PGA gain = 3232
Crosstalk Between ChannelsVCTAIN15–AIN0, VIN = 1VP-P, 10kHz,
RSOURCE = 5kΩ-80dB
Input Common-Mode Rejection
RatioCMRRAIN15–AIN0 (bipolar, differential),VCM = 100mV to 4.5V-70-90dB
Power-Supply Rejection RatioPSRRAVDD = +4.75V to +5.25V6775dB
DAC SECTION (DACOUT, RL = 5kΩ and CL = 100pF)ResolutionNDACGuaranteed monotonic12Bits
Differential NonlinearityDNLDACCode 147h to E68h±0.4±1LSB
Integral NonlinearityINLDACCode 147h to E68h±0.5±4LSB
Offset ErrorReference to code 040h±2.5±30mV
Offset-Error Temperature Coeficient±5µV/°C
Gain ErrorExcludes reference error, tested at E68h±3±20LSB
Gain-Error Temperature CoeficientExcludes offset and reference drift; calculated from FSR±2ppm of FSR/°C
DAC Output RangeNo load0VREFDACV
DC Output ImpedanceZOUTTermination resistance to AGND
DAC enabled0.5Ω
Power-down
mode105kΩ
Output Slew Rate400h to C00h code swing, rising or falling0.6V/µs
Output Settling Time147h to E68h code swing, settling to ±0.5 LSB (Note 5)815µs
Output Short-Circuit CurrentShort to AGND-27mAShort to AVDD46
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Electrical Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDAC Glitch ImpulseFrom 7FFh to 800h12nV·s
DAC Power-On TimeExcluding reference, settling to ±0.5 LSB14µs
Power-Supply RejectionAVDD step from +4.75V to +5.25V62µV/V
Output NoiseCL = 200pF200µVRMS
EXTERNAL REFERENCE INPUTSREFADC Input-Voltage Range1.05.0AVDDV
REFDAC Input-Voltage Range05.0AVDDV
REFDAC Input Impedance200kΩ
REFADC Leakage CurrentADC disabled1µA
TEMPERATURE SENSOR (Remote NPN Transistor 2N3904)Temperature Error
Internal diode
TA = +25°C±1
TA = -30°C to +85°C±2
TA = -40°C to +125°C±5
External diode,differential coniguration(Note 6)
TA = +25°C,
TRJ = +25°C±2
TA = -30°C to +85°C,
TRJ = +25°C±3
TA = -40°C to +125°C,
TRJ = +25°C±3
TA = -30°C to +85°C,
TRJ = -30°C to +85°C±3
TA = -40°C to +125°C,
TRJ = -40°C to +125°C ±5
Internal (Die) or External Temperature Measurement Error vs. VREFADC Variation0.095°C/mV
External Diode Source CurrentHigh level74.7µALow level4
External Diode Drive Current Ratio18.7:1µA/µA
Conversion TimefADCCLK = fSYSCLK = 8MHz, no interrupts, internal utility ROM tempConv70µs
Temperature Resolution12-bit ADC0.125°C/LSB
+3.3V LINEAR REGULATOR (CDVDD = 4.7µF)DVDDIO Input-Voltage Range4.255.05.25V
DVDD Output VoltageREGEN = GNDIO3.03.43.6V
DVDD Input-Voltage RangeREGEN = DVDDIO3.03.6V
No-Load Quiescent CurrentCPU in sleep mode; all digital peripherals
disabled15µA
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Electrical Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SUPPLY VOLTAGE SUPERVISORS AND BROWNOUT DETECTIONDVDD Voltage-Supervisor Reset
Rising Threshold Power-on default, DVDD voltage rising(Note 7)2.702.99V
DVDD Voltage-Supervisor Brownout Reset Falling Threshold VVDBR
DVDD voltage falling, irmware selectable, measured with CPU active at 8MHz(Note 8)
VDBR = 00b (default)2.702.99VDBR = 01b2.773.06
VDBR = 10b2.843.13
VDBR = 11b2.913.20
Software-Selectable DVDD Voltage-Supervisor Brownout Interrupt Falling Threshold VVDBI
DVDD voltage falling, irmware selectable, measured with CPU active at 8MHz(Note 9)
VDBI = 00b (default)2.773.06VDBI = 01b2.843.13
VDBI = 10b2.913.20
VDBI = 11b2.993.27
DVDDIO Voltage-Supervisor Brownout Interrupt Threshold VVIOBI
DVDDIO voltage falling, irmware selectable,measured with CPU active at 8MHz(Note 10)
VIOBI = 00b (default)4.254.74VIOBI = 01b4.304.79
VIOBI = 10b4.354.84
VIOBI = 11b 4.404.89
Voltage-Supervisor Hysteresis DVDD, DVDDIO1%
DVDD Brownout-Interrupt to Brownout Reset Falling Threshold
Voltage difference between VVDBI and VVDBR, time allowing software clean-up before reset asserted, VDBI = 11b and VDBR = 10b
155mV
Voltage Monitor RangeDVDD1.03.6VDVDDIO05.25
DVDD Ramp-Up RateDVDD must rise faster than this rate between +2.7V and +3.0V35mV/ms
RESET Hold TimeAfter DVDD rises above the VVDBR voltage
trip threshold16ms
CAN INTERFACECAN Baud RateCANCLK = 8MHz1Mbps
CANCLK Mean Frequency Error50ppm external crystal error, 8MHz crystal60ppm
CANCLK Total Frequency Error50ppm external crystal error, 8MHz crystal, clock divided and measured over 500µs interval, mean plus peak cycle jitter< 0.5%
HIGH-FREQUENCY CRYSTAL OSCILLATORClock FrequencyUsing external crystal7.68.12MHzExternal clock source7.68.12
Crystal Oscillator Startup Time8MHz crystal10ms
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Electrical Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCrystal Oscillator StabilityExcluding crystal3ppm/V
XIN Input Load Capacitance
HFIC = 00b (default)7HFIC = 01b18
HFIC = 10b27
HFIC = 11b34
XOUT Output Load Capacitance
HFOC = 00b (default)6HFOC = 01b17
HFOC = 10b27
HFOC = 11b34
XIN Input Low VoltageDriven with external clock source0.3 x DVDDV
XIN Input High VoltageDriven with external clock source0.7 x DVDDV
INTERNAL RC OSCILLATOROscillator Frequency7.07.68.0MHz
Oscillator Startup Time10µs
Oscillator Jitter2.7ns
UART (LIN) INTERFACE (UTX, URX)UART Baud Rate02Mbps
Minimum LIN Mode Operation1kbps
Maximum LIN Mode Operation20kbps
UART Baud Rates Error
Crystal clock source-0.5+0.5Using internal RC oscillator before autobaud-14.0+14.0
Using internal RC oscillator after autobaud-0.5+0.5
RESET (RESET)RESET Internal Pullup
ResistancePullup to DVDD305kΩ
RESET Output VoltageHigh, RESET deasserted, no load0.9 x DVDDV
Low, RESET asserted, no load0.4
RESET Input High Voltage0.7 x DVDDV
RESET Input Low Voltage0.3 x DVDDV
DIGITAL INPUTS (P0._, CANRXD, URX, REGEN)Input Low Voltage0.3 x DVDDIOV
Input High Voltage0.7 x V
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Electrical Characteristics (continued)
Note 1: All devices are 100% production tested at TA = +25°C.
Note 2: All analog functions disabled and all digital inputs connected to supply or ground.
Note 3: High-speed mode: CPU and three timers running at 8MHz from an external crystal oscillator, CAN enabled and communi-cating at 500kbps, all other peripherals disabled, all digital I/Os static at DVDDIO or GNDIO.
Note 4: CAN transmitting at 500kbps, one timer output at 500kHz, all active I/Os are loaded with 20pF capacitor, all remaining digi-tal I/Os are at DVDDIO or GNDIO.
Note 5: Guaranteed by design and characterization.
Note 6: Based on diode ideality factor of 1.008.
Note 7: DVDD must rise above VVDBR for RESET to become deasserted. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash).
Note 8: RESET is asserted if DVDD falls below VVDBR. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash).
Note 9: An interrupt is generated if DVDD falls below VVDBI. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash).
Note 10: An interrupt is generated if DVDDIO falls below VVIOBI. Caution: Operation is not guaranteed if DVDDIO or AVDD is below 4.75V, except for the DVDDIO brownout monitor and +3.3V linear regulator, that still operate down to 0V and +4.25V, respectively.
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput Pullup ResistancePullup to DVDDIO400kΩ
Input CapacitanceVIN = GNDIO or DVDDIO15pF
DIGITAL OUTPUTS (P0._, CANTXD, UTX)Output Low VoltageISINK = 1.6mA0.4V
Output High VoltageISOURCE = 1.6mADVDDIO- 0.5V
Output Leakage CurrentI/O pins, three-state-1±0.01+1µA
Output CapacitanceI/O pins, three-state15pF
Output Short-Circuit CurrentShort to DVDDIO = +5.25V29mAShort to GNDIO28
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Electrical Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.)
GPO._ OUTPUT LOW VOLTAGE
vs. SINK CURRENTMAXQ7665A toc02
IOL (mA)
(V)642
TA = -40°C
TA = +125°C
TA = +25°C
TA = +85°C
DAC INL vs. INPUT CODE
(REFDAC = +5V)MAXQ7665A toc03
DIGITAL INPUT CODE
INL (LSB)
DAC DNL vs. INPUT CODE
(REFDAC = +5V)
MAXQ7665A toc04
DIGITAL INPUT CODE
DNL (LSB)
DAC OFFSET VOLTAGE
vs. TEMPERATURE
MAXQ7665A toc05
TEMPERATURE (°C)
OFFSET VOLTAGE (mV)
DAC GAIN ERROR
vs. TEMPERATURE
MAXQ7665A toc06
TEMPERATURE (°C)
GAIN ERROR (LSB)
DAC OFFSET ERROR
vs. AVDD SUPPLY VOLTAGE
MAXQ7665A toc07
DAC OFFSET ERROR (mV)
DACREF = +4.75VDACREF = AVDD
GPO._ OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENTMAXQ7665A toc01
IOH (mA)
(V)64210
TA = +125°C
TA = -40°C
TA = +85°C
TA = +25°C
DAC GAIN ERROR
vs. AVDD SUPPLY VOLTAGEMAXQ7665A toc08
DAC GAIN ERROR (LSB)
DACREF = AVDD
DACREF = +4.75V
DACOUT OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENTMAXQ7665A toc09
(V)312
REFDAC = +5V
OUTPUT CODE = FFFh
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Typical Operating Characteristics
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.)
DACOUT OUTPUT LOW VOLTAGE
vs. SINK CURRENTMAXQ7665A toc10
IOL (mA)
(V)312
REFDAC = +5V
OUTPUT CODE = 000h
DACOUT LARGE-SIGNAL STEP RESPONSE
(CODE 000h TO FFFh)MAXQ7665A toc11
4.0µs/div
DACOUT
(1V/div)
REFDAC = +5V
ADC INL vs. OUTPUT CODE
(REFADC = +5V, 142ksps, PGA GAIN = 16)MAXQ7665A toc12
DIGITAL OUTPUT CODE
ADC INL (LSB)
BIPOLAR MODE
VIN = -156mV TO +156mV
ADC DNL vs. OUTPUT CODE
(REFADC = +5V, 142ksps, PGA GAIN = 16)MAXQ7665A toc13
DIGITAL OUTPUT CODE
ADC DNL (LSB)
BIPOLAR MODE
VIN = -156mV TO +156mV
ADC/PGA OFFSET ERROR (GAIN = 16)
vs. TEMPERATUREMAXQ7665A toc14
TEMPERATURE (°C)
OFFSET ERROR (mV)
ADC/PGA GAIN ERROR (GAIN = 16)
vs. TEMPERATURE
MAXQ7665A toc15
TEMPERATURE (°C)
GAIN ERROR (% FSR)
ADC BIPOLAR ZERO-CODE ERROR
vs. TEMPERATURE
MAXQ7665A toc15b
ZERO-CODE ERROR (mV)
ADC/PGA OFFSET ERROR (GAIN = 16)
vs. AVDD SUPPLY VOLTAGE
MAXQ7665A toc16
OFFSET ERROR (mV)
REFADC = +4.75V
REFADC = AVDD
ADC/PGA GAIN ERROR (GAIN = 16)
vs. AVDD SUPPLY VOLTAGEMAXQ7665A toc17
GAIN ERROR (% FSR)
REFADC = AVDDREFADC = +4.75V
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Typical Operating Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.)
ADC/PGA ZERO-CODE ERROR (GAIN = 16)
vs. AVDD SUPPLY VOLTAGEMAXQ7665A toc17b
AVDD (V)
ZERO-CODE ERROR (mV)
REFADC = +4.75VREFADC = AVDD
INTERNAL DIODE TEMPERATURE-SENSOR
ERROR vs. TEMPERATUREMAXQ7665A toc18
TEMPERATURE (°C)
ERROR (ACTUAL - REPORTED °C)
EXTERNAL DIODE TEMPERATURE-SENSOR
ERROR vs. TEMPERATURE
MAXQ7665A toc19
TEMPERATURE (°C)
ERROR (ACTUAL - REPORTED °C)
REMOTE TEMPERATURE-SENSOR
ERROR DUE TO CAPACITIVE LOADING
MAXQ7665A toc20
CAPACITIVE LOAD BETWEEN AIN0 AND AIN1 (nF)
TEMPERATURE-SENSOR ERROR (°C)1551025
DVDD, RESET POWER-UP
CHARACTERISTICSMAXQ7665A toc21
10ms/div
DVDD
(1V/div)
RESET
(2V/div)
DVBR[1:0] = [0:0]
DVDD, RESET POWER-DOWN
CHARACTERISTICSMAXQ7665A toc22
10ms/div
DVDD
(1V/div)
RESET
(2V/div)
DVBR[1:0] = [0:0]
MAXIMUM DVDD TRANSIENT DURATION
vs. BOR THRESHOLD OVERDRIVEMAXQ7665A toc23
MAXIMUM TRANSIENT DURATION (µs)
BROWNOUT RESET (BOR)
ASSERTED ABOVE THIS LINE
MAXIMUM DVDD TRANSIENT DURATION
vs. BOI THRESHOLD OVERDRIVEMAXQ7665A toc24
MAXIMUM TRANSIENT DURATION (µs)
BROWNOUT INTERRUPT (BOI)
ASSERTED ABOVE THIS LINE
MAXIMUM DVDDIO TRANSIENT DURATION
vs. BOI THRESHOLD OVERDRIVEMAXQ7665A toc25
MAXIMUM TRANSIENT DURATION (µs)
BOI ASSERTED ABOVE THIS LINE
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Typical Operating Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.)
DVDD BOR THRESHOLD VOLTAGE
vs. TEMPERATUREMAXQ7665A toc26
TEMPERATURE (°C)
DVDD-BOR
(V)
DVBR[1:0] = [0:0]
REGEN = DVDDIO
DVDD BOI THRESHOLD VOLTAGE
vs. TEMPERATUREMAXQ7665A toc27
TEMPERATURE (°C)
DVDD-BOI
(V)
DVBI[1:0] = [0:0]
REGEN = DVDDIO
DVDDIO BOI THRESHOLD VOLTAGE
vs. TEMPERATUREMAXQ7665A toc28
TEMPERATURE (°C)
DVDDIO-BOI
(V)
VIOBI[1:0] = [0:0]
DVDD LINEAR REGULATOR OUTPUT
VOLTAGE vs. DVDDIO SUPPLY VOLTAGEMAXQ7665A toc29
DVDDIO (V)
(V)
REGEN = GND
ILOAD = 50mA
ILOAD = 25mA
ILOAD = 0mA
DVDD LINEAR REGULATOR OUTPUT
VOLTAGE vs. TEMPERATUREMAXQ7665A toc30
TEMPERATURE (C)
(V)
ILOAD = +25mA
REGEN = GND
DVDD LINEAR REGULATOR OUTPUT
VOLTAGE vs. LOAD CURRENTMAXQ7665A toc31
LOAD CURRENT (mA)
(V)302010
REGEN = GND
TA = -40°C
TA = +25°C
TA = +125°C
TA = +85°C
DVDD LINEAR REGULATOR OUTPUT
VOLTAGE LINE TRANSIENT
(DVDDIO = +4.75V TO +5.25V STEP)MAXQ7665A toc32
DVDDIO
(200mV/div)
+4.75V
OFFSET
DVDD
(5mV/div)
AC-COUPLED
REGEN = GND
ILOAD = 25mA
DVDD LINEAR REGULATOR OUTPUT
VOLTAGE LOAD TRANSIENT
(IDVDD = 0 TO 50mA STEP)MAXQ7665A toc33
DVDD
(20mV/div)
AC-COUPLED
ILOAD
(50mA/div)
REGEN = GND
DVDD LINEAR REGULATOR DROPOUT
VOLTAGE vs. LOAD CURRENTMAXQ7665A toc34
DROPOUT
(mV)
TA = -40°C
TA = +25°C
VDROPOUT = DVDDIO - DVDD, WHEN
DVDDIO IS LOWERED ENOUGH BELOW
+5V TO MAKE DVDD DROP BY 100mV.
TA = +85°C
TA = +125°C
REGEN = GND
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Typical Operating Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.)
RC OSCILLATOR OUTPUT FREQUENCY
vs. TEMPERATUREMAXQ7665A toc35
TEMPERATURE (°C)
FREQUENCY (MHz)
DVDD = +3.3V
REGEN = DVDDIO
RC OSCILLATOR OUTPUT FREQUENCY
vs. DVDD SUPPLY VOLTAGEMAXQ7665A toc36
DVDD (V)
FREQUENCY (MHz)
REGEN = DVDDIO
DVDD ACTIVE SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGEMAXQ7665A toc37
DVDD (V)
IDVDD
(mA)
SEE NOTES AFTER ELECTRICAL
CHARACTERISTICS TABLE.
FLASH ERASE/PROGRAM
NOTE 3
DVDD ACTIVE SUPPLY CURRENT
vs. TEMPERATUREMAXQ7665A toc38
TEMPERATURE (°C)
DVDD
(mA)
NOTE 3FLASH ERASE/PROGRAM
SEE NOTES AFTER ELECTRICAL
CHARACTERISTICS TABLE.
DVDD STOP-MODE SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGEMAXQ7665A toc39
DVDD SUPPLY VOLTAGE (V)
DVDD
(A)
REGEN = DVDDIO
CPU IN STOP MODE
ALL PERIPHERALS DISABLED
BOR DISABLED
BOR ENABLED
DVDD STOP-MODE SUPPLY CURRENT
vs. TEMPERATUREMAXQ7665A toc40
TEMPERATURE (°C)
IDVDD
(A)
REGEN = DVDDIO
CPU IN STOP MODE
ALL PERIPHERALS DISABLED
BOR DISABLED
BOR ENABLED
AVDD ENABLED SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGEMAXQ7665A toc41
IAVDD
(mA)
ALL ANALOG FUNCTIONS ENABLED
AVDD ENABLED SUPPLY CURRENT
vs. TEMPERATUREMAXQ7665A toc42
IAVDD
(mA)
ALL ANALOG FUNCTIONS ENABLED
AVDD DISABLED SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGEMAXQ7665A toc43
IAVDD
(nA)
ALL ANALOG FUNCTIONS DISABLED
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Typical Operating Characteristics (continued)
(AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.)
AVDD DISABLED SUPPLY CURRENT
vs. TEMPERATUREMAXQ7665A toc44
TEMPERATURE (°C)
AVDD
(nA)
ALL ANALOG FUNCTIONS DISABLED
DVDDIO DYNAMIC SUPPLY CURRENT
vs. DVDDIO SUPPLY VOLTAGEMAXQ7665A toc45
DVDDIO SUPPLY VOLTAGE (V)
IDVDDIO
(A)
CAN COMMUNICATING AT 500kbps
ONE TIMER OUTPUT AT 500kHz
ALL ACTIVE I/O LOADED WITH
20pF CAPACITORS
DVDDIO DYNAMIC SUPPLY CURRENT
vs. TEMPERATUREMAXQ7665A toc46
TEMPERATURE (°C)
IDVDDIO
(A)
CAN COMMUNICATING AT 500kbps
ONE TIMER OUTPUT AT 500kHz
ALL ACTIVE I/O LOADED WITH
20pF CAPACITORS
DVDDIO STATIC SUPPLY CURRENT
vs. DVDDIO SUPPLY VOLTAGEMAXQ7665A toc47
DVDDIO (V)
IDVDDIO
(nA)
ALL DIGITAL I/O STATIC
REGEN = DVDDIO
DVDDIO STATIC SUPPLY CURRENT
vs. TEMPERATUREMAXQ7665A toc48
TEMPERATURE (°C)
IDVDDIO
(nA)
ALL DIGITAL I/O STATIC
REGEN = DVDDIO
AVDD SUPPLY CURRENT
vs. ADC SAMPLING RATEMAXQ7665A toc49
fADC (ksps)
IAVDD
(mA)
PGA DISABLED
AUTOMATIC
SHUTDOWN OFF
PGA DISABLED
AUTOMATIC
SHUTDOWN ONAUTOMATIC
SHUTDOWN
MAX SAMPLING
RATE
AVDD SUPPLY CURRENT
vs. ADC SAMPLING RATE (PGA ENABLED)MAXQ7665A toc50
IAVDD
(mA)
PGA ENABLED
AUTOMATIC
SHUTDOWN OFF
PGA ENABLED
AUTOMATIC
SHUTDOWN ON
SAMPLING ERROR
vs. INPUT SOURCE IMPEDANCEMAXQ7665A toc51
SAMPLING ERROR (LSB)100
PGA GAIN = 32
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Typical Operating Characteristics (continued)
PINNAMEFUNCTIONAIN11Analog Input Channel 11. AIN11 is multiplexed to the PGA as a differential input with AIN10.AIN10Analog Input Channel 10. AIN10 is multiplexed to the PGA as a differential input with AIN11.AIN9Analog Input Channel 9. AIN9 is multiplexed to the PGA as a differential input with AIN8.AIN8Analog Input Channel 8. AIN8 is multiplexed to the PGA as a differential input with AIN9.
5, 8AGNDAnalog GroundREFADCADC External Reference Input. Connect an external reference voltage between 1V and AVDD to REFADC.REFDACDAC External Reference Input. Connect an external reference voltage between 0V and AVDD to REFDAC.AIN7Analog Input Channel 7. AIN7 is multiplexed to the PGA as a differential input with AIN6.AIN6Analog Input Channel 6. AIN6 is multiplexed to the PGA as a differential input with AIN7.AIN5Analog Input Channel 5. AIN5 is multiplexed to the PGA as a differential input with AIN4.AIN4Analog Input Channel 4. AIN4 is multiplexed to the PGA as a differential input with AIN5.AIN3Analog Input Channel 3. AIN3 is multiplexed to the PGA as a differential input with AIN2. AIN3–AIN0 have remote temperature sensor capability.AIN2Analog Input Channel 2. AIN2 is multiplexed to the PGA as a differential input with AIN3. AIN3–AIN0 have remote temperature sensor capability.AIN1Analog Input Channel 1. AIN1 is multiplexed to the PGA as a differential input with AIN0. AIN3–AIN0 have remote temperature sensor capability.AIN0Analog Input Channel 0. AIN0 is multiplexed to the PGA as a differential input with AIN1. AIN3–AIN0 have remote temperature sensor capability.DACOUTDAC Buffer Output. DACOUT is the DAC voltage buffer output.
18, 19, 31DGNDDigital Ground for the Digital Core and FlashCANRXDCAN Bus Receiver Input. Control area network receiver input.CANTXDCAN Bus Transmitter Output. Control area network transmitter output.UTXUART Transmitter OutputURXUART Receiver InputP0.6/T0Port 0 Bit 6/Timer 0. P0.6 is a general-purpose digital I/O with interrupt/wake-up input capability. T0 is a primary timer/PWM input or output.P0.7/T1Port 0 Bit 7/Timer 1. P0.7 is a general-purpose digital I/O with interrupt/wake-up input capability. T1 is a primary timer/PWM input or output.
26, 39DVDDIODigital I/O Supply Voltage. Supplies all digital I/O except for XIN, XOUT, and RESET. Bypass DVDDIO to GNDIO with a 0.1µF capacitor placed as close as possible to the device. DVDDIO is also connected to the input of the linear regulator.GNDIODigital I/O Ground
28, 29I.C.Internal Connection. Connect I.C. to GNDIO or DVDDIO.N.C.No Connection. No internal connection. Leave N.C. unconnected.P0.0/TDOPort 0 Data 0/JTAG Serial Test Data Output. P0.0 is a general-purpose digital I/O with interrupt/wake-up capability. TDO is the JTAG serial test, data output.
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Pin Description
PINNAMEFUNCTIONP0.1/TMSPort 0 Data 1/JTAG Test Mode Select. P0.1 is a general-purpose digital I/O with interrupt/wake-up capability. TMS is the JTAG test mode, select input.P0.2/TDIPort 0 Data 2/JTAG Serial Test Data Input. P0.2 is a general-purpose digital I/O with interrupt/wake-up capability. TDI is the JTAG serial test, data input.P0.3/TCKPort 0 Data 3/JTAG Serial Test Clock Input. P0.3 is a general-purpose digital I/O with interrupt/wake-up capability. TCK is the JTAG serial test, clock input.P0.4/ADCCNVPort 0 Data 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O. ADCCNV is irmware conigurable for a rising or falling edge start/convert to trigger ADC conversions.P0.5/DACLOADPort 0 Data 5/DAC Data Register Load/Update Input. P0.5 is a general-purpose digital I/O with interrupt/wake-up capability. DACLOAD is irmware conigurable for a rising or falling edge to update the DACOUT register.REGENActive-Low Linear Regulator Enable Input. Connect REGEN to GNDIO to enable the linear regulator. Connect to DVDDIO to disable the linear regulator.DVDD
Digital Supply Voltage. DVDD supplies the internal digital core and lash memory. DVDD is internally connected to the output of the internal 3.3V linear regulator. Disable the internal regulator to connect DVDD to an external supply. When using the on-chip linear regulator, bypass DVDD to DGND with a 4.7µF Q20% capacitor with a maximum ESR of 0.5Ω. In addition, bypass DVDD with a 0.1µF capacitor. Place both bypass capacitors as close as possible to the device.RESETReset Input and Output. Active-low open-drain input/output with internal 360kΩ pullup to DVDD. Drive low to reset the µC. RESET is low during power-up reset and during DVDD brownout conditions.XOUTHigh-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation. Leave XOUT unconnected if XIN is driven with an external clock source. XOUT is not driven when using the internal RC oscillator.XINHigh-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for normal operation, or drive XIN with an external clock source. XIN is not driven when using the internal RC oscillator.AVDDAnalog Supply Voltage Input. Connect AVDD to a +5V supply. Bypass AVDD to AGND with a 0.1µF capacitor placed as close as possible to the device.AIN15Analog Input Channel 15. AIN15 is multiplexed to the PGA as a differential input with AIN14.AIN14Analog Input Channel 14. AIN14 is multiplexed to the PGA as a differential input with AIN15.AIN13Analog Input Channel 13. AIN13 is multiplexed to the PGA as a differential input with AIN12.AIN12Analog Input Channel 12. AIN12 is multiplexed to the PGA as a differential input with AIN13.EPExposed Pad. EP is internally connected to AGND. Connect EP to AGND externally.
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Pin Description (continued)
REFADC
17:1
MUX
12-BIT ADC12-BIT DAC
SOFTWARE-
INTERRUPT
CONTROLLER
DVDDIO BROWNOUT
MONITOR
I/O
BUFFERS
1:2 CURRENT
DEMUX
9:1
MUX
DACREF
AIN0
AIN1
AIN2
AIN3
TSE
ADCMX0
AIN4
AIN5
AIN13
AIN12
AIN11
AIN10
AIN14
AIN15
AIN1
AIN3
AIN5
AIN7
AIN9
AIN11
AIN13
AIN15
ADCMX[3.0]
HFFINT
EIFO
UARTI
DVBI
T0I
T1I
T2I
CANSTI
CANERIVIBE
AGND
VIOBI
TEMPERATURE
SENSORS
INTERNAL
IINT
ADCMX3
ADCCLK
ADCE
ADCRYADCOV
GNDIO
DVDDIO
DACE
DACER
DACOUT
REFDAC
P0.6/T0
P0.7/T1
P0.4/ADCCNV
P0.5/DACLOAD
UTX
URXUART
INTERFACE
TIMER2/PWM2
(2 x 8 BITS OR 1 x 16 BITS)
PORT 0
I/O REGISTERS
TIMER1/PWM1
(2 x 8 BITS OR 1 x 16 BITS)
TIMER0/PWM0
(2 x 8 BITS OR 1 x 16 BITS)
T2CLK
T2I
T1CLK
T1I
T0CLK
T0I
UARTI
WATCHDOG
TIMERHFRCCLK
EWT
8KB
UTILITY ROM
16-BIT MAXQ20
RISC CPU32/48/64/128KB
FLASH
512 BYTES
DATA RAM
+3.3V
LINEAR
REGULATOR
DVDD
POWER-ON-
RESET/
BROWNOUT
MONITOR
HF CLOCK
PRESCALER
ADC CLOCK
PRESCALER
CAN CLOCK
PRESCALER
JTAG INTERFACE
PORT 0
I/O REGISTERS
I/O
BUFFERS
GNDIO
XTAL
OSC.
HFRCCLK
TIMER CLOCK
PRESCALERS
XHFE
RCE
INT HF
R-C OSC
SYSCLK
SYSCLK
XHFRY
HFFINT
2:1
DGND16 x 16
MULTIPLY
CAN 2.0B
INTERFACE
I/O
BUFFERSCANSTI
CANERI
GNDIO
CANCLK
CANTXD
CANRXD
GNDIODVDDIO
DVDD
DGND
P0.3/TCK
P0.1/TMS
P0.2/TDI
P0.0/TDO
DVDDIO
REGEN
DVDD
XOUT
GNDIO
DGND
XIN
WDI
DVBIVDPE
VDBE
DVDD
RESET
AVDD
REMOTE
TEMP-SENSE DIODE
CURRENT DRIVE
DVDD
WTR
CANCLK
ADCCLK
T0CLK
T1CLK
T2CLK
AIN6
AIN7
AIN8
AIN9
DGND
GAIN = x1, x2,
x4, x8, x16, x32
PGAPGAE
PD0
PO0
PI0
EIF0
HFCLK
DVDDIO
ADCREF
MAXQ7665A–MAXQ7665DMAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Block Diagram
Detailed DescriptionThe μC arithmetic core of the MAXQ7665A–MAXQ7665D is a 16-bit RISC machine with digital and analog periph-eral functions. They incorporate a 16-bit RISC ALU with a Harvard memory architecture that can address up to 128KB (64K x 16) of flash and 512 bytes (256 x 16) of RAM memory. They also contain a hardware multiplier, up to eight digital I/Os, a controller area network (CAN 2.0B) bus, a JTAG interface, three timers, an on-chip RC oscillator, a precision 12-bit 500ksps ADC with an 8-chan-nel differential MUX and PGA, a 12-bit precision DAC,
an internal temperature sensor and temperature-sensor driver, a linear regulator, watchdog timer, and a dual power-supply supervisor.
The MAXQ offers a low < 3mA/MIPS ratio. The on-chip 16-bit x 16-bit hardware multiplier with accumulator, per-forms single-cycle computations. Refer to the MAXQ7665/
MAXQ7666 User’s Guide for more detailed informa-tion on configuring and programming the MAXQ7665A–MAXQ7665D.
Analog Input PeripheralThe integrated 12-bit ADC employs an ultra-low-power, high-precision, SAR-based conversion method and can operate up to 500ksps (142ksps with PGA ≥ 2). The on-chip 8-channel differential MUX and PGA allow the ADC to measure eight fully differential analog inputs with software-selectable input ranges through the PGA. See Figure 1.
AIN0
AIN2
AIN4
AIN6
AIN8
AIN10
AIN12
AIN14
AIN1
AIN3
AIN5
AIN7
AIN9
AIN11
AIN13
AIN15
P0.4/ADCCNV
CONVERSION
CONTROL
ADCBYTIMERS 0, 1, 2
ADCDUL
ADCS10
PGA
1 TO 32 10
PGG
ADCRDY
ADCOV
ADCBIP
PGAE
ADCE
REFADC
ADC
CLOCK
DIV
ADCASDDATA
BUS 3210
ADCMX10
ADCCD
SYSCLK
SOURCE
8:1
MUX
ADCDIF
12-BIT ADC
500ksps
8:1
MUX
MAXQ7665A–MAXQ7665DMAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
The MAXQ7665A–MAXQ7665D ADC uses a fully dif-ferential SAR conversion technique and an on-chip T/H block to convert temperature and voltage signals into a 12-bit digital result. Differential configurations are sup-
ported using an analog input channel MUX that supports eight differential channels.
The differential analog inputs are selected from the follow-ing pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13, and AIN14/AIN15.
Remote temperature-sensor configuration in differential mode uses analog input channel pairs AIN2/AIN3 and AIN0/AIN1. In single-ended remote temperature-sensor con-figuration, only channels AIN2 and AIN0 are used. Internal temperature-sensor configuration measures local die tem-perature and does not use any analog input channel.
There are four ways to control the ADC conversion timing:
1) Software register bit control
2) Continuous conversion
3) Internal timers (T0, T1, or T2)
4) External input through pin ADCCNV
Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information on the ADC and MUX.
12-Bit Digital-to-Analog Converter (DAC)The MAXQ7665A–MAXQ7665D contain a 12-bit voltage-output DAC with its own output buffer. The data path to the DAC is double buffered and the output register can be updated using the DACLOAD digital input. Refer to the
MAXQ7665/MAXQ7666 User’s Guide for detailed pro-gramming information. The DAC also supports a square-wave-output toggle mode with precise amplitude control for applications that require pulse-amplitude modulation (PAM) and/or pulse-width modulation (PWM) signals. See Figure 2 for a simplified block diagram of the DAC.
The DAC output buffer is in a voltage follower configu-ration (gain of 1V/V from REFDAC). The buffer can be disabled when not in use. When the buffer is disabled, the output is connected internally to AGND through a 100kΩ resistor. The reference input REFDAC accepts an input voltage of less than or equal to AVDD for a maximum out-put swing of 0V to AVDD.
Temperature SensorThe μC measures temperature by using the on-chip ADC and a ROM-based tempConv subroutine. Use the temp-Conv subroutine to initiate a measurement (refer to the
MAXQ7665/MAXQ7666 User’s Guide for detailed informa-tion). The device supports conversions of two external and one on-chip (internal) temperature sensors. The external
temperature sensor is typically a diode-connected small-signal transistor, connected between two analog inputs (differential) or one analog input and AGND (single-ended). Figures 3 and 4 illustrate these two configurations.
Figure 2. Simplified DAC Diagram
REFDAC
DACE
DAC INPUT
REGISTER
P0.5/
DACLOAD
DACOUT
DAC OUTPUT
REGISTER12-BIT DAC
DAC LOAD
CONTROL
MAXQ7665A–MAXQ7665DMAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
Power-On Reset and BrownoutPower supplies DVDD and DVDDIO each include a brown-out monitor that alerts the μC through interrupt when their corresponding supply voltages drop below a select-able threshold. This condition is generally referred to as brownout interrupt (BOI), and these thresholds are set by the VDBI and VIOBI bits for DVDD and DVDDIO, respec-tively. Continuous monitoring ensures that a valid supply is present at all times while the μC is executing code.
For example, the brownout monitors check that DVDDIO does not drop during a CAN bus transfer, or DVDD is not disrupted while the μC core is executing. The DVDDIO brownout monitor also covers the analog peripherals if AVDD and DVDDIO are directly connected.
The DVDD supply (internal core logic) also includes a volt-age supervisor that controls the μC reset during power-up (DVDD rising) and brownout (DVDD falling) conditions (see Figure 5 for a POR and brownout timing example).
Figure 3. Temperature-Sensor Application Circuit—Single-Ended Configuration
Figure 4. Temperature-Sensor Application Circuit—Differential Configuration
ADCMX3
MUX
2N3904
CURRENT
SOURCES
ADCMX
AIN15
AIN3
AIN2
AIN1
AIN0
AGND3210
12-BIT ADC
500ksps
2N3904
MAXQ7665A–MAXQ7665DADCMX3
MUX
2N3904
CURRENT
SOURCES
2N3904
ADCMX
AIN15
AIN4
AIN2
AIN3
AIN0
AIN1
AGND43210
12-BIT ADC
500ksps
MAXQ7665A–MAXQ7665DMAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
During power-up, RESET is held low once DVDD rises above +1.0V. All internal register bits are set to their default, POR state after DVDD exceeds a threshold of approximately +1.2V. This includes the VDBR bits which reset to 00b, resulting in a default, DVDD brownout reset (BOR) threshold in the +2.7V to +2.99V range follow-ing POR. Once DVDD rises above this DVDD brownout threshold, the 7.6MHz RC oscillator starts driving the power-up counter, and 8.6ms (typ) later, the RESET pin is released and allowed to go high if nothing external is holding it low. An important system-design consideration at power-up is the DVDD ramp-up rate should be at least 35mV/ms between +2.7V and +3.0V. This ensures
RESET is not released before DVDD reaches a minimum flash operating level of +3.0V. After DVDD has reached a valid level and RESET is released, the μC jumps to the
reset vector (8000h in the utility ROM), and the desired BOI and BOR threshold values can be set by the user through the VIOBI, VDBI, and VDBR bits.
If a valid DVDD drops below its BOI threshold (set by the VDBI bits), an interrupt is generated. This offers the pos-sibility of limited software cleanup before the DVDD BOR occurs. The amount of cleanup time depends on the VDBI and VDBR brownout threshold bit settings, the size of the DVDD bypass capacitors, and the application-dependent, μC power management and software cleanup tasks. Note that if the internal, +3.3V linear regulator is being used to provide DVDD, additional software cleanup time is pos-sible by using the DVDDIO brownout monitor as an early warning that the regulator’s DVDDIO (+5V) input voltage is falling, and its DVDD (+3.3V) will subsequently drop (unless DVDDIO recovers).
Figure 5. DVDD Brownout Interrupt Detection
DGND
NOMINAL
DVDD (+3.3V)
BROWNOUT
RESET
+3.06V
+2.77V
INTERNAL RESETBOR STATE
RESET OUTPUT
DVDD BROWNOUT
INTERRUPT
THRESHOLD RANGE
VDBI[1:0] = 01+3.13V
+2.84V
BROWNOUT
RESET
TRIGGER
POINT
BROWNOUT
INTERRUPT
TRIGGER
POINT
BROWNOUT
INTERRUPT
DVLVL FLAG
(ASR[14])
POWER-UP*
DELAY
(8.6ms)
DVBI FLAG
(ASR[4])
FLAG ARBITRARILY
CLEARED BY µC
*POWER-UP DELAY IS ONLY
PRESENT WHEN DVDD DROPS
BELOW ~1.2V
VDBE BIT SET BY mC
DVDD BROWNOUT
RESET THRESHOLD
RANGE VDBR[1:0] = 01
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
As DVDD continues to fall below the DVDD BOR threshold set by the VDBR bits, the RESET pin is pulled low, μC and peripheral activity stops, and most, but not all of the register bits are set to their default state. This includes the VDBR bits, which retain their value if DVDD falls below the BOR threshold, but not below the POR threshold.
Once DVDD has entered BOR, there are a few possible scenarios:If DVDD remains below the BOR threshold, the RESET pin remains low, and the μC remains in the reset state.If DVDD stops falling before reaching the POR thresh-old, then begins rising above the BOR threshold, the
RESET pin is released, and the μC jumps to the reset vector (8000h in the utility ROM). This is similar to the DVDD power-up case described in the previous sce-nario, except there is no power-up counter delay and some of the register bits are set to BOR values rather than POR values. See Tables 3 and 5 for the reset behavior of specific bits. In particular, the retained VDBR setting, if higher than the default value of 00b, allows a potentially more robust brownout recovery closer to or above the minimum flash operating level of +3.0V.If DVDD falls below the 1.2V POR threshold, all register bits are reset, and any DVDD recovery from that point is identical to the power-up case described above. See Tables 3 and 5 for reset behavior of specific bits.
Refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed programming information, and a more thorough description of POR and brownout behavior.
Internal 3.3V Linear RegulatorThe MAXQ7665A–MAXQ7665D core logic supply, DVDD, can be supplied by a 3.3V external supply or the on-chip 3.3V, 50mA linear regulator. To use the on-chip linear reg-ulator, ensure the DVDDIO supply can support a load of approximately 50mA and connect digital input REGEN to GNDIO. If using an external supply, connect the regulated 3.3V supply to DVDD and connect digital input REGEN to DVDDIO. If the linear regulator is not used, bring up DVDDIO before DVDD.
System Clock GeneratorThe MAXQ7665A–MAXQ7665D oscillator module is the master clock generator that supplies the system clock for the μC core and all of the peripheral modules. The high-frequency (HF) oscillator is designed to operate with an 8MHz crystal. Alternatively, the on-chip RC oscillator can be used in applications that do not require precise timing.
execute most instructions in a single SYSCLK period. The oscillator module contains all of the primary clock-generation circuitry. Figure 6 shows a block diagram of the system clock module.
The MAXQ7665A–MAXQ7665D contain many features for generating a master clock signal timing source:Internal, fast-starting, 7.6MHz RC oscillator eliminates external crystalInternal high-frequency oscillator that can drive an external 8MHz crystalExternal high-frequency clock input (8MHz)Selectable internal capacitors for HF crystal oscillatorPower-up timerPower-saving management modesFail-safe modes
Watchdog TimerThe watchdog timer serves as a time-base generator, an event timer, or a system supervisor. The primary function of the watchdog timer is to supervise software execution, watching for stalled or stuck software. The watchdog timer performs a controlled system restart when the μP fails to write to the watchdog timer register before a selectable timeout interval expires. In some designs, the watchdog
timer is also used to implement a real-time operating system (RTOS) in the μC. When used to implement an RTOS, a watchdog timer typically has four objectives:
1) To detect if a system is operating normally
2) To detect an infinite loop in any of the tasks
3) To detect an arbitration deadlock involving two or more
tasks
4) To detect if some lower priority tasks are not getting to run because of higher priority tasks
CD0
SYSCLKMUX
HFRCCLK
CLOCK
DIVIDE
XTAL
OSC
OSC
XIN
XOUTEXTHFRCE
HFE
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
As illustrated in Figure 7, the high-frequency internal RC oscillator (HFRCCLK) drives the watchdog timer through a series of dividers. The divider output is programmable and determines the timeout interval. When enabled, the interrupt flag WDIF is set when a timeout is reached. A system reset then occurs after a time delay (based on the divider ratio).
The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. The interrupt timeout has a default divide ratio of 212 of the HFRCCLK,
with the watchdog reset set to timeout 29 clock cycles later. With the nominal RC oscillator value of 7.6MHz, an interrupt timeout occurs every 539μs, followed by a watchdog reset 67.4μs later. The watchdog timer is reset to the default divide ratio following any reset. Using the WD0 and WD1 bits in the WDCN register, other divide ratios can be selected for longer watchdog interrupt peri-ods. If the WD[1:0] bits are changed before the watchdog interrupt timeout occurs (i.e. before the watchdog reset counter begins), the watchdog timer count is reset. All watchdog timer reset timeouts follow the programmed interrupt timeout 512 source clock cycles later. For more information on the MAXQ7665A–MAXQ7665D watchdog timer, refer to the MAXQ7665/MAXQ7666 User’s Guide.
Timer and PWMThe MAXQ7665A–MAXQ7665D include three 16-bit timer channels. Each timer is a type 2 timer implemented in the MAXQ family (see Figure 8). Two of the timers are acces-
sible through I/Os, and one is accessible only through software. Type 2 timers are auto-reload 16-bit timers/counters offering the following functions:8-bit/16-bit timer/counterUp/down auto-reloadCounter function of external pulseCaptureCompareFigure 7. Watchdog Functional Diagram
EWDI
WD0RWT
WD1
HFRCCLK
(7.6MHz)
INTERRUPT
WTRF
RESET
WDIF
TIMEOUT
TIME
DIV 212DIV 23DIV 23DIV 23
EWT
RESET
EDGE
DETECTION AND
GATING
TIMER EVENT
CCF[1:0]
G2EN
TR2
SS2
T2POL[0]
T2CL
T2MD
T2L COMPARE MATCH
T2H:T2L COMPARE MATCH OR
T2H COMPARE MATCH
T2L OVERFLOW
T2H:T2L OVERFLOW OR
T2H OVERFLOW
TR2L
T2CLK
T2L
T2RL
T2CH
T2H
T2RH
C/T2
MAXQ7665A–MAXQ7665D16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
