MC100E142FN ,5V ECL 9-Bit Shift Register
MC100E142FN ,5V ECL 9-Bit Shift Register
MC100E142FN ,5V ECL 9-Bit Shift Register
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MC100E142FN
5V ECL 9-Bit Shift Register
D3 D4 VCCO Q0 Q1 Q2VCCOD5D6D7D8SEL
CLK1
CLK2
VEE
S-IN
VCC
VCCO
LOGIC DIAGRAMS-IN
SEL
CLK1
CLK2
* All VCC and VCCO pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA -
The MC10E/100E142 is a 9-bit shift register, designed with byte-parity
applications in mind. The E142 performs serial/parallel in and
serial/parallel out, shifting in one direction. The nine inputs D0–D8
accept parallel input data, while S-IN accepts serial input data. The Qn
outputs do not need to be terminated for the shift operation to function. To
minimize noise and power, any Q output not used should be left
unterminated. 700MHz Min. Shift Frequency 9-Bit for Byte-Parity Applications Asynchronous Master Reset Dual Clocks Extended 100E VEE Range of – 4.2V to – 5.46V 75kΩ Input Pulldown Resistors
The SEL (Select) input pin is used to switch between the two modes of
operation — SHIFT and LOAD. The shift direction is from bit 0 to bit 8.
Input data is accepted by the registers a set-up time before the positive
going edge of CLK1 or CLK2; shifting is also accomplished on the positive
clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets
all the resisters to zero.
PIN NAMES
FUNCTIONS
