mc100EL14DW ,1:5 Clock Distribution Chip** * ** ** * **The High Speed Solution for theCMOS/TTL Designer
MC100EL14DW ,1:5 Clock Distribution Chip**SEMICONDUCTOR TECHNICAL DATA ** The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip ..
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MC100EL14DW
1:5 Clock Distribution Chip
SEMICONDUCTOR TECHNICAL DATA -
The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. The LVEL14 is
functionally and pin compatible with the EL14 but is designed to operate
in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or
3.0V to 3.8V). If a single-ended input is to be used the VBB output should
be connected to the CLK input and bypassed to ground via a 0.01μF
capacitor. The VBB output is designed to act as the switching reference
for the input of the LVEL14 under single-ended input conditions, as a
result this pin can only source/sink up to 0.5mA of current.
The LVEL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by the input
pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This avoids
any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock, therefore
all associated specification limits are referenced to the negative edge of
the clock input. 50ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input 75kΩ Internal Input Pulldown Resistors >2000V ESD Protection VEE Range of –3.0V to –5.5V
LOGIC DIAGRAM AND PINOUT ASSIGNMENT Q2 Q3 Q4
VCCQ3Q2Q1 SCLK CLK CLK VBB SEL VEE
VCC
PIN DESCRIPTION
FUNCTION TABLE On next negative transition of CLK or SCLK
