MC10EP116FA ,3.3V / 5V Hex Differential Line Receiver / Driver3MC10EP116, MC100EP11610EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6)CC EE–40°C 25°C 85° ..
MC10EP116FAR2 ,3.3V / 5V Hex Differential Line Receiver / Driver
MC10EP116FAR2 ,3.3V / 5V Hex Differential Line Receiver / DriverAND8009/DECLinPS PlusSPICE Modeling KitPrepared by:Senad Lomigora, Paul ShockmanON Semiconductor B ..
MC10EP11D ,3.3V / 5V 1:2 Differential Fanout Bufferlogic diagram. It is unnecessary to include an ESD or8−Lead TSSOP 24package model for the V pins of ..
MC10EP11DG , 3.3V / 5V ECL 1:2 Differential Fanout Buffer
MC10EP11DR2 ,3.3V / 5V 1:2 Differential Fanout Bufferfeatures of an ECL device make itrequirement stems only from the speed performance aspectideal for ..
MC34063AMR1 ,DC-to-DC Converter Control CircuitsMAXIMUM RATINGSRating Symbol Value UnitPower Supply Voltage V 40 VdcCCComparator Input Voltage Rang ..
MC34063AMR2 ,DC-to-DC Converter Control CircuitsELECTRICAL CHARACTERISTICS (V = 5.0 V, T = T to T [Note 3.], unless otherwise specified.)CC A low ..
MC34063AN , DC-DC Converter Control Circuits
MC34063AP ,SMPS ControllerMaximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
MC34063AP1 ,DC-to-DC CONVERTER CONTROL CIRCUITSOrder this document by MC34063A/D DC–to–DC CONVERTER** ** **CONTROL CIRCUITSThe MC34063A Series is ..
MC34063AP-1 ,DC-to-DC CONVERTER CONTROL CIRCUITSOrder this document by MC34063A/D DC–to–DC CONVERTER** ** **CONTROL CIRCUITSThe MC34063A Series is ..
MC10EP116FA
3.3V / 5V Hex Differential Line Receiver / Driver
MC10EP116, MC100EP116
3.3V / 5V�Hex Differential
Line Receiver/Driver
The MC10EP116/100EP116 is a 6-bit differential line receiver
based on the EP16 device. The 3.0 GHz bandwidth provided by the
high frequency outputs makes the device ideal for buffering of very
high speed oscillators.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single–ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 �F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
The differential inputs have internal clamp structures which will
force the Q output of a gate in an open input condition to go to a LOW
state. Thus, inputs of unused gates can be left open and will not affect
the operation of the rest of the device. Note that the input clamp will
take affect only if both inputs fall 2.5 V below VCC.
The 100 Series contains temperature compensation. 260 ps Typical Propagation Delay Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V
with VEE = –3.0 V to –5.5 V Open Input Default State Safety Clamp on Inputs Q Output Will Default LOW with Inputs Open or at VEE VBB Output
